CP1610

The CPU used in the Intellivision Master Component is a General Instruments CP1610. The CP1610 is a general purpose microprocessor capable of supporting 16-bit addresses and 10-bit instructions.

Overview

Clock Speed	894,886.25 Hz
Address Width	16-bit
Instruction Width	10-bit
Reset Address	$1000
Interrupt Address	$1004
Flags	S, Z, O, C, I, D
Registers	Eight 16-bit Registers, R0-R7

General Behavior

The R7 register behaves as program counter for the CP1610. On the Intellivision, the CP1610 initializes R7 to the value $1000. The CP1610 then reads, decodes, and executes the opcode at the location reference by R7 and the increments R7 to the next instruction. Although most opcodes are only one memory location in length (one 10-bit value or "decle"), a few opcodes stretch to two or three memory locations, causing R7 to increment by more than a single value in order to find the next instruction to execute. The CP1610 repeats this behavior indefinitely, or until a HLT instruction is read.

The processor also receives hardware interrupts from the STIC which occur once per screen refresh and cause the CP1610 to jump to the interrupt subroutine located at $1004 in the Executive ROM. The STIC may also request the CP1610 temporarily halt processing to allow the STIC to perform direct memory accesses.

Flags

S	Sign Flag	If set, indicates that the previous operation resulted in negative value, which is determined by a one (1) in bit 15 of the result.
C	Carry Flag	If set, indicates that the previous operation resulted in unsigned integer overflow.
Z	Zero Flag	If set, indicates that the previous operation resulted in zero.
O	Overflow Flag	If set, indicates that the previous operation gave a signed result that is inconsistent with the signs of the source operands. (Signed overflow.)
I	Interrupt Enable Flag	If set, allows the INTRM line to trigger an interrupt, causing the CPU to jump to the interrupt subroutine located in the Executive ROM at $1004.
D	Double Byte Data Flag	If set, it causes the next instruction to read a 16-bit operand with two 8-bit memory accesses, if it supports it.

Special notes:

• The S, C, Z, and O flags are directly visible to the programmer via the GSWD instruction. The I and D flags are internal to the CPU, and not visible directly visible to the programmer.
• The C and O flags serve a secondary purpose for the shift and rotate instructions. The SLLC, SARC, RLC and RRC use the C and O flags to store bits that get "shifted away." Also, the RLC and RRC instructions "shift in" the bits stored in C and O.
• The S flag takes on a special role also with the shift instructions. The SWAP, SLR, SAR, SARC and RRC instructions set the S flag based on bit 7 of the result, rather than bit 15.
  
  

Signal Pins

Signal	Name	Direction	Purpose	Use on Intellivision
INTRM	INTerrupt Request, Masked.	Input	A high-to-low transition on this pin causes the CPU to take an interrupt if interrupts are enabled. If the signal transitions back to the "high" state prior to taking the interrupt, the CPU will ignore the interrupt.	Connects to the SR1 output pin on the STIC. The STIC signals VBlank Interrupt to the CP1610 on this pin, and the CP1610 jumps to the interrupt vector at $1004 after the next interruptible instruction.
INTR	INTerrupt Request.	Input	A high-to-low transition on this pin causes the CPU to take an interrupt, regardles of whether interrupts are enabled.	The Intellivision leaves this signal tied to +5v (deasserted).
BUSRQ	BUS ReQuest.	Input	A high-to-low transition on this pin requests that the CPU halt so that something else may access the bus.	Connects to the SR2 output pin on the STIC. The STIC signals the CP1610 on this pin at points during active display when it needs to access System RAM. The CP1610 halts after the next interruptible instruction, regardless of whether interrupts are enabled.
BUSAK	BUS AcKnowledge.	Output	Asserted (active-low output) when the CPU has yielded the bus.	Connects to the SST input pins on the System RAM and the GROM. The CP1610 acknowledges the STIC's bus request by signaling to the System RAM and GROM that it halted by request of the STIC.
MSYNC	Master SYNC.	Input	Asserting this signal (active low) resets the CPU and synchronizes it to its clocks.	Connects to the MSYNC output of the STIC. The STIC generates this signal shortly after powerup after the clock stabilizes, or whenever someone releases the reset button or asserts RESET on the cartridge port.
EBCA0 - EBCA3	External Branch Condition Address.	Output	The four outputs EBCA0 through EBCA3, along with the single input ECBI provide a mechanism for external hardware to generate branch control inputs to the CPU. The BEXT instruction includes a 4-bit field that the CP1610 asserts on EBCA0 - EBCA3. External hardware then asserts a 0 or 1 on EBCI to indicate whether to take the branch. This allows up to 16 different branch conditions to be asserted to the CPU.	These pins are not connected in the Intellivision, so the BEXT instruction is typically never used.
EBCI	External Branch Condition Input.	Input
TCI	Terminate Current Interrupt.	Output	TCI is both an instruction as well as a pin on the device. The TCI instruction pulses the TCI pin on the CP1610.	The Intellivision leaves this signal unconnected, and so the TCI instruction is effectively a NOP.
PCIT	Program Counter Inhibit/Trap.	Bidirectional.	External hardware can prevent the CPU from incrementing the program counter by asserting this signal. The SIN instruction generates a pulse on this line.	The Intellivision leaves this signal tied to +5v (deasserted) through a resistor.
STPST	SToP-STart.	Input	Stops or starts the execution of the CPU whenever it sees a high-to-low transition.	The Intellivision leaves this signal tied to +5v.
HALT	HALTed.	Output	Indicates the CPU halted.	The Intellvision leaves this signal unconnected.
BDRDY	Bus Data ReaDY.	Input	When deasserted, it causes the CPU to wait for data to become available on the bus, effectively inserting wait states.	The Intellivision leaves this signal unconnected, and thus has no notion of wait states.

Interruptibility

Each CP1610 opcode is considered either "interruptible" or "not interruptible". The interruptibility of an opcode determines whether or not the CP1610 checks the status of INTRM and BUSRQ after executing that instruction, and prior to executing the next. The CP1610 will check for an interrupt request signaled via INTRM only if both the Interrupt Enable Flag flag is set and previous instruction was an interruptible instruction. It is important to understand that the Interrupt Enable Flag and the interruptibility of each opcode are completely separate functions and both work together to prevent or allow the CP1610 to accept interrupts on the INTRM line. For more information on interrupts, see the VBlank Interrupt topic.

Similarly, the CP1610 only receives a signal from the STIC via BUSRQ for a total of exactly 114 CP1610 clock cycles. Although unaffected by the status of the I flag, if the CP1610 nonetheless encounters a stream of uninterruptible instructions, it will miss the chance to halt altogether and will fail to signal back to the STIC on BUSAK. The STIC, in turn, will fail to perform the necessary direct memory accesses to fetch the next row of cards to display. The exact behavior of the Intellivision hardware is unknown if this occurs, but it is believed to likely render a duplicate of the previous row of cards.

Registers

There are eight 16-bit registers available in the CP1610, labelled R0-R7.

R0	General Purpose.
R1	General Purpose.
R2	General Purpose.
R3	General Purpose.
R4	General Purpose. Auto-Incrementing.
R5	General Purpose. Auto-Incrementing.
R6	General Purpose. Auto-Incrementing. Auto-Decrementing.
R7	Program Counter. Auto-Incrementing.

Instruction Set

Below is a detailed breakdown of all the opcodes available as a part of the CP1610 instruction set. Click on each opcode for more information.

Range	Instruction	Mnemonic	Cycles	Interruptible	Input Flags	Output Flags
$0000	Halt	HLT	NA	No
$0001	Set Double Byte Data	SDBD	4	No		D
$0002	Enable Interrupt System	EIS	4	No		I
$0003	Disable Interrupt System	DIS	4	No		I
$0004	Jump	J/JD/JE JSR/JSRD/JSRE	7/9	Yes		I
$0005	Terminate Current Interrupt	TCI
$0006	Clear Carry	CLRC	4	No		C
$0007	Set Carry	SETC	4	No		C
$0008-$000F	Increment Register	INCR
$0010-$0017	Decrement Register	DECR
$0018-$001F	Complement Register	COMR
$0020-$0027	Negate Register	NEGR
$0028-$002F	Add Carry to Register	ADCR
$0030-$0033	Get the Status Word	GSWD
$0034-$0035	No Operation	NOP
$0036-$0037	Software Interrupt	SIN
$0038-$003F	Return Status Word	RSWD
$0040-$0047	Swap Bytes	SWAP
$0048-$004F	Shift Logical Left	SLL
$0050-$0057	Rotate Left through Carry	RLC
$0058-$005F	Shift Logical Left through Carry	SLLC
$0060-$0067	Shift Logical Right	SLR
$0068-$006F	Shift Arithmetic Right	SAR
$0070-$0077	Rotate Right through Carry	RRC
$0078-$007F	Shift Arithmetic Right through Carry	SARC
$0080-$00BF	Move Register	MOVR
$00C0-$00FF	Add Registers	ADDR
$0100-$013F	Subtract Registers	SUBR
$0140-$017F	Compare Registers	CMPR
$0180-$01BF	And Registers	ANDR
$01C0-$01FF	Xor Registers	XORR
$0200-$021F	Branch	B/BC/BOV/BPL BEQ/BLT/BLE/BUSC NOPP/BNC/BNOV/BMI BNEQ/BGE/BGT/BESC
$0220-$023F		BEXT
$0240-$0247	Move Out	MVO
$0248-$027F	Move Out Indirect	MVO@
$0280-$0287	Move In	MVI
$0288-$02BF	Move In Indirect	MVI@
$02C0-$02C7	Add	ADD
$02C8-$02FF	Add Indirect	ADD@
$0300-$0307	Subtract	SUB
$0308-$033F	Subtract Indirect	SUB@
$0340-$0347	Compare	CMP
$0348-$037F	Compare Indirect	CMP@
$0380-$0387	And	AND
$0388-$03BF	And Indirect	AND@
$03C0-$03C7	Xor	XOR
$03C8-$03FF	Xor Indirect	XOR@