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The CPU used in the Intellivision is a General Instruments CP1610. The CP1610 is a general purpose microprocessor capable of supporting 16-bit addresses and 10-bit instructions.


Clock Speed894,886.25 Hz (NTSC)
Address Width16-bit
Instruction Opcode Width10-bit
Reset Address$1000
Interrupt Address$1004
FlagsS, Z, O, C, I, D
RegistersEight 16-bit Registers, R0-R7

General Behavior

The R7 register behaves as program counter for the CP1610. On the Intellivision, the CP1610 initializes R7 to the value $1000. The CP1610 then reads, decodes, and executes the opcode at the location reference by R7 and the increments R7 to the next instruction. Although most opcodes are only one memory location in length (one 10-bit value or "decle"), a few opcodes stretch to two or three memory locations, causing R7 to increment by more than a single value in order to find the next instruction to execute. The CP1610 repeats this behavior indefinitely, or until a HLT instruction is read.

The processor also receives hardware interrupts from the STIC which occur once per screen refresh and cause the CP1610 to jump to the interrupt subroutine located at $1004 in the Executive ROM. The STIC may also request the CP1610 temporarily halt processing to allow the STIC to perform direct memory accesses.


SSign FlagIf set, indicates that the previous operation resulted in negative value, which is determined by a one (1) in bit 15 of the result.
CCarry FlagIf set, indicates that the previous operation resulted in unsigned integer overflow.
ZZero FlagIf set, indicates that the previous operation resulted in zero.
OOverflow FlagIf set, indicates that the previous operation gave a signed result that is inconsistent with the signs of the source operands. (Signed overflow.)
IInterrupt Enable FlagIf set, allows the INTRM line to trigger an interrupt, causing the CPU to jump to the interrupt subroutine located in the Executive ROM at $1004.
DDouble Byte Data FlagIf set, it causes the next instruction to read a 16-bit operand with two 8-bit memory accesses, if it supports it.

Special notes:

  • The S, C, Z, and O flags are directly visible to the programmer via the GSWD instruction. The I and D flags are internal to the CPU, and not visible directly visible to the programmer.
  • The C and O flags serve a secondary purpose for the shift and rotate instructions. The SLLC, SARC, RLC and RRC use the C and O flags to store bits that get "shifted away." Also, the RLC and RRC instructions "shift in" the bits stored in C and O.
  • The S flag takes on a special role also with the shift instructions. The SWAP, SLR, SAR, SARC and RRC instructions set the S flag based on bit 7 of the result, rather than bit 15.

Signal Pins

SignalNameDirectionPurposeUse on Intellivision
INTRMINTerrupt Request, Masked.Input A high-to-low transition on this pin causes the CPU to take an interrupt if interrupts are enabled. If the signal transitions back to the "high" state prior to taking the interrupt, the CPU will ignore the interrupt.Connects to the SR1 output pin on the STIC. The STIC signals VBlank Interrupt to the CP1610 on this pin, and the CP1610 jumps to the interrupt vector at $1004 after the next interruptible instruction.
INTRINTerrupt Request.Input A high-to-low transition on this pin causes the CPU to take an interrupt, regardless of whether interrupts are enabled.The Intellivision leaves this signal tied to +5v (deasserted).
BUSRQBUS ReQuest.Input A high-to-low transition on this pin requests that the CPU halt so that something else may access the bus. Connects to the SR2 output pin on the STIC. The STIC signals the CP1610 on this pin at points during active display when it needs to access System RAM. The CP1610 halts after the next interruptible instruction, regardless of whether interrupts are enabled.
BUSAKBUS AcKnowledge.Output Asserted (active-low output) when the CPU has yielded the bus. Connects to the SST input pins on the System RAM and the GROM. The CP1610 acknowledges the STIC's bus request by signaling to the System RAM and GROM that it halted by request of the STIC.
MSYNCMaster SYNC.Input Asserting this signal (active low) resets the CPU and synchronizes it to its clocks. Connects to the MSYNC output of the STIC. The STIC generates this signal shortly after powerup after the clock stabilizes, or whenever someone releases the reset button or asserts RESET on the cartridge port.
EBCA0 - EBCA3External Branch Condition Address.Output The four outputs EBCA0 through EBCA3, along with the single input ECBI provide a mechanism for external hardware to generate branch control inputs to the CPU. The BEXT instruction includes a 4-bit field that the CP1610 asserts on EBCA0 - EBCA3. External hardware then asserts a 0 or 1 on EBCI to indicate whether to take the branch. This allows up to 16 different branch conditions to be asserted to the CPU. These pins are not connected in the Intellivision, so the BEXT instruction is typically never used.
EBCIExternal Branch Condition Input.Input
TCITerminate Current Interrupt.Output TCI is both an instruction as well as a pin on the device. The TCI instruction pulses the TCI pin on the CP1610. The Intellivision leaves this signal unconnected, and so the TCI instruction is effectively a NOP.
PCITProgram Counter Inhibit/Trap.Bidirectional. External hardware can prevent the CPU from incrementing the program counter by asserting this signal. The SIN instruction generates a pulse on this line. The Intellivision leaves this signal tied to +5v (deasserted) through a resistor.
STPSTSToP-STart.InputStops or starts the execution of the CPU whenever it sees a high-to-low transition. Can restart the CPU after a HLT instruction.The Intellivision leaves this signal tied to +5v.
HALTHALTed.OutputIndicates the CPU halted, either due to STPST or a HLT instruction.The Intellivision leaves this signal unconnected.
BDRDYBus Data ReaDY.InputWhen deasserted, it causes the CPU to wait for data to become available on the bus, effectively inserting wait states.The Intellivision leaves this signal unconnected, and thus has no notion of wait states.


Each CP1610 opcode is considered either "interruptible" or "not interruptible". The interruptibility of an opcode determines whether or not the CP1610 checks the status of INTRM and BUSRQ after executing that instruction, and prior to executing the next. The CP1610 will check for an interrupt request signaled via INTRM only if both the Interrupt Enable Flag flag is set and previous instruction was an interruptible instruction. It is important to understand that the Interrupt Enable Flag and the interruptibility of each opcode are completely separate functions and both work together to control when the CP1610 accepts interrupts on the INTRM line. For more information on interrupts, see the VBlank Interrupt topic.

Similarly, the STIC only asserts BUSRQ to the CP1610 for 114 CP1610 clock cycles (on NTSC systems). The Interrupt Enable Flag does not affect the CPU's ability to respond to this bus request. Non-interruptible instructions, however, do. Thus, if a program contains an extended sequence of non-interruptible instructions, the CPU will not halt in time for the System RAM to prepare the next row of display cards. Instead, the machine will duplicate the previous row and push the rest of the display down. It appears that the CPU must halt within about 57 cycles of BUSRQ first being asserted in order to prevent display glitches.


There are eight 16-bit registers available in the CP1610, labelled R0-R7.

Register NameDescription
R0General Purpose.
R1General Purpose.
R2General Purpose.
R3General Purpose.
R4General Purpose. Auto-increments on indirect reads and writes.
R5General Purpose. Auto-increments on indirect reads and writes.
R6SPStack Pointer. Auto-increments on indirect reads. Auto-decrements on indirect writes.
R7PCProgram Counter. Auto-increments on indirect reads and writes.

The names "SP" and "PC" are assembler aliases for "R6" and "R7," respectively. They may be used interchangeably.

Addressing Modes

The CP1610 supports several addressing modes. Click on any of the addressing modes below for more information.

ImpliedThe opcode's inputs or outputs are implied by the opcode itself.
RegisterThe value to be read or written is contained in one or more registers. No memory access are required to execute Register-mode opcodes.
DirectThe address of the value to be read or written is specified by the value immediately following the address of the opcode.
ImmediateThe address of the value to be read or written is the address immediately following the opcode. Note that immediate mode addressing is really just Indirect addressing using the R7 register.
IndirectThe address of the value to be read or written is contained in one of the registers.
StackThis Indirect Mode through R6, the stack pointer.

Instruction Set

Below is a detailed breakdown of all the opcodes available as a part of the CP1610 instruction set. Click on each opcode for more information. Also, you might look at the original GI Instruction Set Reference, which is a handy (if occasionally incomplete or inaccurate) guide.

RangeInstructionMnemonic(s)CyclesInterruptibleInput FlagsOutput Flags
$0001Set Double Byte DataSDBD4NoD
$0002Enable Interrupt SystemEIS4NoI
$0003Disable Interrupt SystemDIS4NoI
$0005Terminate Current InterruptTCI4No
$0006Clear CarryCLRC4NoC
$0007Set CarrySETC4NoC
$0008-$000FIncrement RegisterINCR6YesSZ
$0010-$0017Decrement RegisterDECR6YesSZ
$0018-$001FComplement RegisterCOMR6YesSZ
$0020-$0027Negate RegisterNEGR6YesSZOC
$0028-$002FAdd Carry to RegisterADCR6YesCSZOC
$0030-$0033Get the Status WordGSWD6YesSZOC
$0034-$0035No OperationNOP6Yes
$0036-$0037Software InterruptSIN6Yes
$0038-$003FReturn Status WordRSWD6YesSZOC
$0040-$0047Swap BytesSWAP6/8NoSZ
$0048-$004FShift Logical LeftSLL6/8NoSZ
$0050-$0057Rotate Left through CarryRLC6/8NoOCSZOC
$0058-$005FShift Logical Left through CarrySLLC6/8NoOCSZOC
$0060-$0067Shift Logical RightSLR6/8NoSZ
$0068-$006FShift Arithmetic RightSAR6/8NoSZ
$0070-$0077Rotate Right through CarryRRC6/8NoOCSZOC
$0078-$007FShift Arithmetic Right through CarrySARC6/8NoOCSZOC
$0080-$00BFMove RegisterMOVR6/7YesSZ
$00C0-$00FFAdd RegistersADDR6YesSZOC
$0100-$013FSubtract RegistersSUBR6YesSZOC
$0140-$017FCompare RegistersCMPR6YesSZOC
$0180-$01BFAnd RegistersANDR6YesSZ
$01C0-$01FFXor RegistersXORR6YesSZ
$0240-$0247Move OutMVO11No
$0248-$026FMove Out IndirectMVO@9NoD
$0270-$027FMove Out ImmediateMVOI9NoD
$0280-$0287Move InMVI10Yes
$0288-$02AFMove In IndirectMVI@8/10/11YesD
$02B0-$02BFMove In ImmediateMVII8/10YesD
$02C8-$02EFAdd IndirectADD@8/10/11YesDSZOC
$02F0-$02FFAdd ImmediateADDI8/10YesDSZOC
$0308-$032FSubtract IndirectSUB@8/10/11YesDSZOC
$0330-$033FSubtract ImmediateSUBI8/10YesDSZOC
$0348-$036FCompare IndirectCMP@8/10/11YesDSZOC
$0370-$037FCompare ImmediateCMPI8/10YesDSZOC
$0388-$03AFAnd IndirectAND@8/10/11YesDSZ
$03B0-$03BFAnd ImmediateANDI8/10YesDSZ
$03C8-$03EFXor IndirectXOR@8/10/11YesDSZ
$03F0-$03FFXor ImmediateXORI8/10YesDSZ