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Instruction NameShift Logical Left Through Carry
CP1610 Clock Cycles6 or 8
Opcode Range$0058-$005F
Input FlagsNone
Output FlagsSign Flag, Zero Flag, Overflow Flag, Carry Flag

The Shift Logical Left Through Carry (SLLC) instruction shifts the bits in the specified register by either one (1) or two (2) bits to the left, stores the result back to the specified register, and sets or clears the Sign Flag and Zero Flag according to the new value in the register. For either a single or double shift, the Carry Flag is set to the value of bit 15 before the shift occurred. For a double shift, the Overflow Flag is also set to the value of bit 14 before the shift occurred. The rightmost one or two bits are set to zero(0). The number of clock cycles used depends on the number of shifts specified. One shift will use 6 clock cycles and two shifts will use 8 clock cycles.

Sllc diagram.png

The opcode format is as follows.

where: s indicates the number of places to shift such that: s == 0 indicates to shift once s == 1 indicates to shift twice
rr indicates the target register such that: rrr == 000 indicates register R0 rrr == 001 indicates register R1 rrr == 010 indicates register R2 rrr == 011 indicates register R3