Difference between revisions of "Memory Map"
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(→address ranges for other periphs; tweak description of bus float) |
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==Official Memory Map== | ==Official Memory Map== | ||
− | The "official" memory map published by Mattel is included below. | + | The "official" memory map published by Mattel is included below. |
− | |||
<table border width=80%> | <table border width=80%> | ||
<tr><th>Memory Range<th>Accessibility<th>Device</th></tr> | <tr><th>Memory Range<th>Accessibility<th>Device</th></tr> | ||
Line 12: | Line 11: | ||
<tr><td>$3800-$39FF</td><td>RW, [[VBlank Period 2]]</td><td>[[Graphics RAM]]</td></tr> | <tr><td>$3800-$39FF</td><td>RW, [[VBlank Period 2]]</td><td>[[Graphics RAM]]</td></tr> | ||
</table> | </table> | ||
+ | <br/> | ||
+ | The Intellivision uses a bidirectional data bus with external pull-up resistors. Each peripheral on the bus (including the CPU) goes to a "high-impedance" state whenever it is not actively driving a value onto the bus. Thus, if the CPU attempts to read from a memory location and no peripheral responds by asserting a value on the bus, the CPU will see all ones (1)—the 16-bit value $FFFF.<br/><br/> | ||
+ | |||
+ | Mattel had also reserved additional address ranges for various periperals, such as the [[Keyboard Component]], the [[PlayCable]], and the [[Intellivoice]]. Many of these reserved address ranges went effectively unused, and so aren't shown. Each peripheral's address map is documented with the peripheral itself. | ||
==Additional Memory Aliases== | ==Additional Memory Aliases== |
Revision as of 07:33, 11 January 2005
Official Memory Map
The "official" memory map published by Mattel is included below.
Memory Range | Accessibility | Device |
---|---|---|
$0000-$003F | RW, VBlank Period 1 | STIC Registers |
$0100-$01EF | RW | Scratchpad RAM |
$01F0-$01FF | RW | PSG Registers |
$0200-$035F | RW | System RAM |
$1000-$1FFF | R | Executive ROM |
$3000-$37FF | R, VBlank Period 2 | Graphics ROM |
$3800-$39FF | RW, VBlank Period 2 | Graphics RAM |
The Intellivision uses a bidirectional data bus with external pull-up resistors. Each peripheral on the bus (including the CPU) goes to a "high-impedance" state whenever it is not actively driving a value onto the bus. Thus, if the CPU attempts to read from a memory location and no peripheral responds by asserting a value on the bus, the CPU will see all ones (1)—the 16-bit value $FFFF.
Mattel had also reserved additional address ranges for various periperals, such as the Keyboard Component, the PlayCable, and the Intellivoice. Many of these reserved address ranges went effectively unused, and so aren't shown. Each peripheral's address map is documented with the peripheral itself.
Additional Memory Aliases
Note that the official memory map shown above is actually incomplete, due to the fact that the STIC and the Graphics RAM chip incompletely decoded addresses that were placed on the address bus.
Memory Range | Accessibility | Device |
---|---|---|
$3A00-$3BFF | RW, VBlank Period 2 | Graphics RAM |
$3C00-$3DFF | RW, VBlank Period 2 | Graphics RAM |
$3E00-$3FFF | RW, VBlank Period 2 | Graphics RAM |
$4000-$403F | W, VBlank Period 1 | STIC Registers |
$7800-$79FF | W, VBlank Period 2 | Graphics RAM |
$7A00-$7BFF | W, VBlank Period 2 | Graphics RAM |
$7C00-$7DFF | W, VBlank Period 2 | Graphics RAM |
$7E00-$7FFF | W, VBlank Period 2 | Graphics RAM |
$8000-$803F | W, VBlank Period 1 | STIC Registers |
$B800-$B9FF | W, VBlank Period 2 | Graphics RAM |
$BA00-$BBFF | W, VBlank Period 2 | Graphics RAM |
$BC00-$BDFF | W, VBlank Period 2 | Graphics RAM |
$BE00-$BFFF | W, VBlank Period 2 | Graphics RAM |
$C000-$C03F | W, VBlank Period 1 | STIC Registers |
$F800-$F9FF | W, VBlank Period 2 | Graphics RAM |
$FA00-$FBFF | W, VBlank Period 2 | Graphics RAM |
$FC00-$FDFF | W, VBlank Period 2 | Graphics RAM |
$FE00-$FFFF | W, VBlank Period 2 | Graphics RAM |