VBlank Period 1
The STIC allows access to its control registers only certain time periods as part of its vertical refresh. These time periods are anchored relative to the VBlank Interrupt that the STIC generates and the Bus Copy mode that the System RAM implements.
When the display's active, the STIC registers are available for approximately 2900 cycles following the VBlank Interrupt. When the display is not active--that is, the program did not write to location $0020 (or its aliases at $4020, $8020 or $C020) during this 2900 cycle period--the STIC registers remain active until the program requests an active display.
This period is shorter than VBlank Period 2, probably due to internal limitations of the STIC.
No data is presently available for these systems. Given the lower refresh rate and higher clock rate of these systems, both VBlank Period 1 and VBlank Period 2 are probably longer than they are on the NTSC systems. New games should design for the tighter NTSC time windows.