Double Byte Data
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The Set Double Byte Data instruction sets the Double Byte Data Flag (D). This flag causes the next instruction, if it is an Indirect Mode or Immediate Mode instruction, to issue two memory reads instead of one, and construct a 16-bit operand from the lower 8 bits of each value it read. The CPU ignores whatever is in the upper 8 bits of each value read. The first read fills the lower 8 bits of the result, and the second read fills the upper 8 bits. SDBD also modifies the behavior of Direct Mode accesses.
For Immediate mode accesses, the CPU reads the two locations immediately following the instruction. This allows ROMs narrower than 16 bits to hold immediate constants up to 16 bits long. The following diagram illustrates:
For Indirect mode accesses, if the indirect register is auto-incrementing (R4 or R5), the two values read come from consecutive addresses, as shown:
If the indirect register is not auto-incrementing (R1, R2 or R3), the instruction reads the same location twice.
The CP1610 does not specifically support SDBD with Indirect accesses through the stack pointer. Programs also must be careful not to use the same register both as a numeric operand and an indirect register when accessing Double Byte Data. In both of these cases, strange behavior results.
Note that the D flag only remains set for the next executed opcode, regardless of whether of not the next opcode is actually affected by the status of the Double Byte Data Flag. After execution of the next opcode, the CPU clears the Double Byte Data Flag automatically. As a result, SDBD acts as like a prefix instruction.
The Double Byte Data Flag affects the behavior of the following instructions:
The D flag also changes the timing of the instruction it modifies. Generally, it adds 2 cycles to most Indirect and Immediate instructions. Thus, where MVI@ might take 8 cycles, SDBD + MVI@ takes 14: 4 for the SDBD, 10 for the MVI@ modified by the D flag.