Difference between revisions of "CP1610"
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==Signal Pins== | ==Signal Pins== | ||
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− | <tr><td>INTRM</td><td> | + | <tr><td>INTRM</td><td>INTerrupt Request, Masked. Pulsing this pin low causes the CPU to take an interrupt if interrupts are enabled. The Intellivision connects this pin to the SR1 output pin on the STIC. The STIC signals [[VBlank Interrupt]] to the CP1610 on this pin, and the CP1610 jumps to the interrupt vector at $1004 after the next interruptible instruction.</td></tr> |
− | <tr><td>BUSRQ</td><td> | + | <tr><td>INTR</td><td>INTerrupt Request. Pulsing this pin low causes the CPU to take an interrupt, regardles of whether interrupts are enabled. The Intellivision leaves this signal tied to +5v (deasserted).</td></tr> |
− | <tr><td>BUSAK</td><td> | + | <tr><td>BUSRQ</td><td>BUS ReQuest. Pulsing this pin low requests that the CPU halt so that something else may access the bus. The Intellivision connects this to the SR2 output pin on the STIC. The STIC signals the CP1610 on this pin at points during active display when it needs to access [[System RAM]]. The CP1610 halts after the next interruptible instruction, regardless of whether interrupts are enabled.</td></tr> |
− | + | <tr><td>BUSAK</td><td>BUS AcKnowledge. The Intellivision connects this output pin to the SST input pin on the System RAM and the [[Graphics ROM|GROM]]. The CP1610 acknowledges the STIC's bus request by signaling to the System RAM and GROM that it halted by request of the STIC.</td></tr> | |
+ | <tr><td>MSYNC</td><td>Master SYNC. Asserting this input resets the CPU. In the Intellivision, the STIC generates this signal shortly after powerup after the clock stabilizes, or whenever someone releases the reset button or asserts RESET on the cartridge port.</td></tr> | ||
<tr><td>ECBA0 - ECBA3, ECBI</td><td>The four outputs ECBA0 through ECBA3, along with the single input ECBI provide a mechanism for external hardware to generate branch control inputs to the CPU. The BEXT instruction includes a 4-bit field that the CP1610 asserts on ECBA0 - ECBA3. External hardware then asserts a 0 or 1 on ECBI to indicate whether to take the branch. These pins are not connected in the Intellivision, so the BEXT instruction is typically never used.</td></tr> | <tr><td>ECBA0 - ECBA3, ECBI</td><td>The four outputs ECBA0 through ECBA3, along with the single input ECBI provide a mechanism for external hardware to generate branch control inputs to the CPU. The BEXT instruction includes a 4-bit field that the CP1610 asserts on ECBA0 - ECBA3. External hardware then asserts a 0 or 1 on ECBI to indicate whether to take the branch. These pins are not connected in the Intellivision, so the BEXT instruction is typically never used.</td></tr> | ||
<tr><td>TCI</td><td>Terminate Current Interrupt. TCI is both an instruction as well as a pin on the device. The TCI instruction pulses the TCI pin on the CP1610. The Intellivision leaves this signal unconnected, and so the TCI instruction is effectively a NOP.</td></tr> | <tr><td>TCI</td><td>Terminate Current Interrupt. TCI is both an instruction as well as a pin on the device. The TCI instruction pulses the TCI pin on the CP1610. The Intellivision leaves this signal unconnected, and so the TCI instruction is effectively a NOP.</td></tr> | ||
<tr><td>PCIT</td><td>Program Counter Inhibit/Trap. This signal is bidirectional. External hardware can prevent the CPU from incrementing the program counter by asserting this signal. The SIN instruction generates a pulse on this line. The Intellivision leaves this signal tied to +5v (deasserted) through a resistor.</td></tr> | <tr><td>PCIT</td><td>Program Counter Inhibit/Trap. This signal is bidirectional. External hardware can prevent the CPU from incrementing the program counter by asserting this signal. The SIN instruction generates a pulse on this line. The Intellivision leaves this signal tied to +5v (deasserted) through a resistor.</td></tr> | ||
− | + | <tr><td>STPST</td><td>SToP-STart. A negative-edge triggered input that stops or starts the execution of the CPU. The Intellivision leaves this signal tied to +5v.</td></tr> | |
+ | <tr><td>HALT</td><td>Output that indicates the CPU halted. The Intellvision leaves this signal unconnected.</td></tr> | ||
+ | <tr><td>BDRDY</td><td>Bus Data ReaDY. When deasserted, it causes the CPU to wait for data to become available on the bus, effectively inserting wait states. The Intellivision leavs this signal unconnected.</td></tr> | ||
</table><br/> | </table><br/> | ||
Revision as of 00:59, 11 January 2005
The CPU used in the Intellivision Master Component is a General Instruments CP1610. The CP1610 is a general purpose microprocessor capable of supporting 16-bit addresses and 10-bit instructions.
Contents
Overview
Clock Speed | 894,886.25 Hz |
Address Width | 16-bit |
Instruction Width | 10-bit |
Reset Address | $1000 |
Interrupt Address | $1004 |
Flags | S, Z, O, C, I, D, inter |
Registers | R0, R1, R2, R3, R4, R5, R6, R7 |
Signal Pins | INTRM, BUSRQ, BUSAK |
External Pins | EXT |
General Behavior
The R7 register behaves as program counter for the CP1610. On the Intellivision, the CP1610 initializes R7 to the value $1000. The CP1610 then reads, decodes, and executes the opcode at the location reference by R7 and the increments R7 to the next instruction. It repeats this behavior indefinitely, or until a HLT instruction is read.
Although most opcodes are only one memory location in length (one 10-bit value or "decle"), a few opcodes stretch to two or three memory locations, causing R7 to increment by more than a single value in order to find the next instruction to execute. The processor receives hardware interrupts from the STIC which occur once per screen refresh. The STIC may also request the CP1610 temporarily halt processing to allow the STIC to perform direct memory accesses.
Flags
S | Sign Flag. If set, indicates that the previous operation resulted in negative value. |
C | Carry Flag. If set, indicates that the previous operation resulted in a number too large to be contained in a single register. |
Z | Zero Flag. If set, indicates that the previous operation resulted in zero. |
O | Overflow Flag. If set, indicates that the previous operation resulted in an overflow or underflow. |
I | Interrupt Enable Flag. If set, allows the INTRM line to trigger an interrupt, causing the CPU to jump to the interrupt subroutine located in the Executive ROM at $1004. |
D | Double Data Flag. If set, causing the next opcode, if it is capable of operating on a 16-bit operand, to load the 16-bit operand from the lowest 8 bits of two consecutive memory locations, rather than all 16-bits of a single memory location. |
Signal Pins
INTRM | INTerrupt Request, Masked. Pulsing this pin low causes the CPU to take an interrupt if interrupts are enabled. The Intellivision connects this pin to the SR1 output pin on the STIC. The STIC signals VBlank Interrupt to the CP1610 on this pin, and the CP1610 jumps to the interrupt vector at $1004 after the next interruptible instruction. |
INTR | INTerrupt Request. Pulsing this pin low causes the CPU to take an interrupt, regardles of whether interrupts are enabled. The Intellivision leaves this signal tied to +5v (deasserted). |
BUSRQ | BUS ReQuest. Pulsing this pin low requests that the CPU halt so that something else may access the bus. The Intellivision connects this to the SR2 output pin on the STIC. The STIC signals the CP1610 on this pin at points during active display when it needs to access System RAM. The CP1610 halts after the next interruptible instruction, regardless of whether interrupts are enabled. |
BUSAK | BUS AcKnowledge. The Intellivision connects this output pin to the SST input pin on the System RAM and the GROM. The CP1610 acknowledges the STIC's bus request by signaling to the System RAM and GROM that it halted by request of the STIC. |
MSYNC | Master SYNC. Asserting this input resets the CPU. In the Intellivision, the STIC generates this signal shortly after powerup after the clock stabilizes, or whenever someone releases the reset button or asserts RESET on the cartridge port. |
ECBA0 - ECBA3, ECBI | The four outputs ECBA0 through ECBA3, along with the single input ECBI provide a mechanism for external hardware to generate branch control inputs to the CPU. The BEXT instruction includes a 4-bit field that the CP1610 asserts on ECBA0 - ECBA3. External hardware then asserts a 0 or 1 on ECBI to indicate whether to take the branch. These pins are not connected in the Intellivision, so the BEXT instruction is typically never used. |
TCI | Terminate Current Interrupt. TCI is both an instruction as well as a pin on the device. The TCI instruction pulses the TCI pin on the CP1610. The Intellivision leaves this signal unconnected, and so the TCI instruction is effectively a NOP. |
PCIT | Program Counter Inhibit/Trap. This signal is bidirectional. External hardware can prevent the CPU from incrementing the program counter by asserting this signal. The SIN instruction generates a pulse on this line. The Intellivision leaves this signal tied to +5v (deasserted) through a resistor. |
STPST | SToP-STart. A negative-edge triggered input that stops or starts the execution of the CPU. The Intellivision leaves this signal tied to +5v. |
HALT | Output that indicates the CPU halted. The Intellvision leaves this signal unconnected. |
BDRDY | Bus Data ReaDY. When deasserted, it causes the CPU to wait for data to become available on the bus, effectively inserting wait states. The Intellivision leavs this signal unconnected. |
Interruptibility
Each CP1610 opcode is considered either "interruptible" or "not interruptible". The interruptibility of an opcode determines whether or not the CP1610 checks the status of INTRM and BUSRQ. The CP1610 will only check for an interrupt request signaled via INTRM only if the I flag is set and only after the next interruptible instruction. Note that the signal from the STIC via INTRM is only alive for the duration of vertical blank, exactly 3,791 CP1610 clock cycles. If the I flag is clear for that entire duration, or if the CP1610 never encounters an interruptible instruction during that time, the CP1610 will miss the interrupt altogether. I have personally noticed this as a problem in particular for the game Dreadnaught Factor.
Similarly, the CP1610 only receives a signal from the STIC via BUSRQ for a total of exactly 114 CP1610 clock cycles. Although unaffected by the status of the I flag, if the CP1610 nonetheless encounters a stream of uninterruptible instructions, it will miss the chance to halt altogether and will fail to signal back to the STIC on BUSAK. The STIC, in turn, will fail to perform the necessary direct memory accesses to fetch the next row of cards to display. The exact behavior of the Intellivision hardware is unknown if this occurs, but it is believed to likely render a duplicate of the previous row of cards.
Registers
TBD
Instruction Set
Below is a detailed breakdown of all the opcodes available as a part of the CP1610 instruction set. This information is somewhat incomplete at the moment, but will be filled out a bit more in the near future.
Range | Instruction | Mnemonic | Opcode | Flags |
---|---|---|---|---|
$0000 | HaLT | HLT | 0000:0000:0000:0000 | |
$0001 | Set DouBle Data | SDBD | 0000:0000:0000:0001 | |
$0002 | Enable InterruptS | EIS | 0000:0000:0000:0010 | |
$0003 | Disable InterruptS | DIS | 0000:0000:0000:0011 | |
$0004 | Jump | J/JD/JE/J@ JSR/JSRD/JSRE/JSR@ | 0000:0000:0000:0100 | |
$0005 | ??? | TCI | 0000:0000:0000:0101 | |
$0006 | CLeaR Carry | CLRC | 0000:0000:0000:0110 | |
$0007 | SET Carry | SETC | 0000:0000:0000:0111 | |
$0008-$000F | INCrement Register | INCR | 0000:0000:0000:1rrr rrr = target register | |
$0010-$0017 | DECrement Register | DECR | 0000:0000:0001:0rrr rrr = target register | |
$0018-$001F | COMplement Register | COMR | 0000:0000:0001:1rrr rrr = target register | |
$0020-$0027 | NEGate Register | NEGR | 0000:0000:0010:0rrr rrr = target register | |
$0028-$002F | ADd Carry to Register | ADCR | 0000:0000:0010:1rrr rrr = target register | |
$0030-$0033 | Get the Status WorD | GSWD | 0000:0000:0011:00rr rr = target register | |
$0034-$0035 | No OPeration | NOP | 0000:0000:0011:010x x = ignored | |
$0036-$0037 | ??? | SIN | 0000:0000:0011:011x x = ignored | |
$0038-$003F | Retrieve Status WorD | RSWD | 0000:0000:0011:1rrr rrr = target register | |
$0040-$0047 | SWAP bytes | SWAP | 0000:0000:0100:0srr s: 0 = swap once, 1 = swap twice rr = target register | |
$0048-$004F | Shift Logical Left | SLL | 0000:0000:0100:1srr s = shift count rr = target register | |
$0050-$0057 | Rotate Left with Carry | RLC | 0000:0000:0101:0srr s = rotate count rr = target register | |
$0058-$005F | Shift Logical Left with Carry | SLLC | 0000:0000:0101:1srr s = shift count rr = target register | |
$0060-$0067 | Shift Logical Right | SLR | 0000:0000:0110:0srr s = shift count rr = target register | |
$0068-$006F | Shift Arithmetic Right | SAR | 0000:0000:0110:1srr s = shift count rr = target register | |
$0070-$0077 | Rotate Right with Carry | RRC | 0000:0000:0111:0srr s = rotate count rr = target register | |
$0078-$007F | Shift Arithmetic Right with Carry | SARC | 0000:0000:0111:1srr s = shift count rr = target register | |
$0080-$00BF | MOVe Right | MOVR | 0000:0000:10ss:sddd sss = source register ddd = destination register | |
$00C0-$00FF | ADD Registers | ADDR | 0000:0000:11ss:sddd sss = source register ddd = destination register | |
$0100-$013F | SUBtract Registers | SUBR | 0000:0001:00ss:sddd sss = source register ddd = destination register | |
$0140-$017F | CoMPare Registers | CMPR | 0000:0001:01ss:sddd sss = source register ddd = destination register | |
$0180-$01BF | AND Registers | ANDR | 0000:0001:10ss:sddd sss = source register ddd = destination register | |
$01C0-$01FF | XOR Registers | XORR | 0000:0001:11ss:sddd sss = source register ddd = destination register | |
$0200-$023F | Branch | B/BC/BOV/BPL BEQ/BLT/BLE/BUSC NOPP/BNC/BNOV/BMI BNEQ/BGE/BGT/BESC BEXT | 0000:0010:00de:nccc d = direction e = external n = negation ccc = condition | |
$0240-$0247 | MoVe Out | MVO | 0000:0010:0100:0rrr rrr = register to move | |
$0248-$027F | MoVe Out Indirect | MVO@ | 0000:0010:01ss:srrr sss = register with address (not zero) rrr = register to move | |
$0280-$0287 | MoVe In | MVI | 0000:0010:1000:0rrr rrr = register to move | |
$0288-$02BF | MoVe In Indirect | MVI@ | 0000:0010:01ss:srrr sss = register with address (not zero) rrr = register to move | |
$02C0-$02C7 | ADD | ADD | 0000:0010:0100:0rrr rrr = register to store result | |
$02C8-$02FF | ADD Indirect | ADD@ | 0000:0010:01ss:srrr sss = register with address (not zero) rrr = register to move | |
$0300-$0307 | SUBtract | SUB | 0000:0010:0100:0rrr rrr = register to store result | |
$0308-$033F | SUBtract Indirect | SUB@ | 0000:0010:01ss:srrr sss = register with address (not zero) rrr = register to move | |
$0340-$0347 | CoMPare | CMP | 0000:0010:0100:0rrr rrr = register to store result | |
$0348-$037F | CoMPare Indirect | CMP@ | 0000:0010:01ss:srrr sss = register with address (not zero) rrr = register to move | |
$0380-$0387 | AND | AND | 0000:0010:0100:0rrr rrr = register to store result | |
$0388-$03BF | AND Indirect | AND@ | 0000:0010:01ss:srrr sss = register with address (not zero) rrr = register to move | |
$03C0-$03C7 | XOR | XOR | 0000:0010:0100:0rrr rrr = register to store result | |
$03C8-$03FF | XOR Indirect | XOR@ | 0000:0010:01ss:srrr sss = register with address (not zero) rrr = register to store result |