MVII

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m (Protected "MVII" ([edit=autoconfirmed] (indefinite) [move=autoconfirmed] (indefinite)))
 
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[[Category:CP1610]]
[[Category:CP1610]]
<table border>
<table border>
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<tr><td>Instruction Name</td><td>Move In Indirect</td></tr>
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<tr><td>Instruction Name</td><td>Move In Immediate</td></tr>
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<tr><td>Mnemonic</td><td>MVI@</td></tr>
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<tr><td>Mnemonic</td><td>MVII</td></tr>
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<tr><td>CP1610 Clock Cycles</td><td>8, 10, or 11</td></tr>
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<tr><td>CP1610 Clock Cycles</td><td>8, 10</td></tr>
<tr><td>Interruptible</td><td>Yes</td></tr>
<tr><td>Interruptible</td><td>Yes</td></tr>
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<tr><td>Opcode Range</td><td>$0288-$02Bf</td></tr>
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<tr><td>Opcode Range</td><td>$02B0-$02BF</td></tr>
<tr><td>Input Flags</td><td>[[Double Byte Data Flag]]</td></tr>
<tr><td>Input Flags</td><td>[[Double Byte Data Flag]]</td></tr>
<tr><td>Output Flags</td><td>None</td></tr>
<tr><td>Output Flags</td><td>None</td></tr>
</table><br/>
</table><br/>
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The Move In Indirect (MVI@) instruction copies the value from the address contained in the specified address register into the specified destination register.  Assuming the [[Double Byte Data Flag]] is <strong>clear</strong>, then this instruction will use 8 clock cycles <strong>unless</strong> R6 is used as the address register, in which case it will use 11 clock cycles.<br/><br/>
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The Move In Immediate (MVII) instruction copies the value at the address immediately following the opcode to the specified destination register.  Note that this instruction is really just a variant of the [[MVI@|Move In Indirect]] instruction using R7 as the address register. See the [[MVI@|Move In Indirect]] documentation for more information.<br/>
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If the [[Double Byte Data Flag]] is set, then this instruction will perform two indirect reads, using the lowest 8 bits of the first read as the lowest 8 bits of the resulting value and combining them with the lowest 8 bits of the second read as the highest 8 bits of the resulting value. Note that if the address register is R0-R3 (which do <strong>not</strong> auto-increment or auto-decrement), then the register value will not change between successive indirect reads, and thus the same value at the same address would be read for both indirect reads.  If the [[Double Byte Data Flag]] is set, this instruction will always use exactly 10 clock cycles regardless of which register is used as the address register.<br/>
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     0000:0010:1011:1ddd<br/>
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     0000:0010:10aa:addd<br/>
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     where:
     where:
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         ddd  indicates the register containing the value to move
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         ddd  indicates the destination register
               such that:
               such that:
                   ddd == 000    indicates register R0
                   ddd == 000    indicates register R0
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                   ddd == 110    indicates register R6
                   ddd == 110    indicates register R6
                   ddd == 111    indicates register R7<br/>
                   ddd == 111    indicates register R7<br/>
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        aaa  indicates the register containing the address
 
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              such that:
 
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                  aaa == 000    indicates register R0
 
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                  aaa == 001    indicates register R1
 
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                  aaa == 010    indicates register R2
 
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                  aaa == 011    indicates register R3
 
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                  aaa == 100    indicates register R4
 
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                  aaa == 101    indicates register R5
 
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                  aaa == 110    indicates register R6
 
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                  aaa == 111    indicates register R7<br/>
 

Latest revision as of 08:54, 4 December 2010

Instruction NameMove In Immediate
MnemonicMVII
CP1610 Clock Cycles8, 10
InterruptibleYes
Opcode Range$02B0-$02BF
Input FlagsDouble Byte Data Flag
Output FlagsNone

The Move In Immediate (MVII) instruction copies the value at the address immediately following the opcode to the specified destination register. Note that this instruction is really just a variant of the Move In Indirect instruction using R7 as the address register. See the Move In Indirect documentation for more information.

   0000:0010:1011:1ddd
where: ddd indicates the destination register such that: ddd == 000 indicates register R0 ddd == 001 indicates register R1 ddd == 010 indicates register R2 ddd == 011 indicates register R3 ddd == 100 indicates register R4 ddd == 101 indicates register R5 ddd == 110 indicates register R6 ddd == 111 indicates register R7
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