AND@

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Instruction NameAnd Indirect
MnemonicAND@
CP1610 Clock Cycles8, 10, or 11
InterruptibleYes
Opcode Range$0388-$03AF
Input FlagsNone
Output FlagsSign Flag, Zero Flag

The And Indirect (AND@) instruction performs a bitwise AND between the value at the address in the specified address register and the value in the specified destination register, stores the result in the destination register, and sets or clears the Sign Flag and Zero Flag according to the result.

If the Double Byte Data Flag is set, then this instruction will perform two indirect reads, using the lowest 8 bits of the first read as the lowest 8 bits of the resulting value and combining them with the lowest 8 bits of the second read as the highest 8 bits of the resulting value. Note that if the address register is R1-R3 (which do not auto-increment or auto-decrement), then the register value will not change between successive indirect reads, and thus the same value at the same address would be read for both indirect reads. If the Double Byte Data Flag is set, this instruction will always use exactly 10 clock cycles regardless of which register is used as the address register.


   0000:0011:10aa:addd
where: ddd indicates the register containing the value to move such that: ddd == 000 indicates register R0 ddd == 001 indicates register R1 ddd == 010 indicates register R2 ddd == 011 indicates register R3 ddd == 100 indicates register R4 ddd == 101 indicates register R5 ddd == 110 indicates register R6 ddd == 111 indicates register R7
aaa indicates the register containing the address such that: aaa == 000 indicates register R0 aaa == 001 indicates register R1 aaa == 010 indicates register R2 aaa == 011 indicates register R3 aaa == 100 indicates register R4 aaa == 101 indicates register R5 aaa == 110 indicates register R6 aaa == 111 indicates register R7
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