SLR - Revision history

Mr z: Protected "SLR" ([edit=autoconfirmed] (indefinite) [move=autoconfirmed] (indefinite))

2010-12-04T09:12:08Z

Protected "SLR" ([edit=autoconfirmed] (indefinite) [move=autoconfirmed] (indefinite))

Mr z at 14:54, 8 October 2007

2007-10-08T14:54:33Z

Mr z at 07:19, 15 January 2005

2005-01-15T07:19:59Z

Pingaso at 17:22, 14 January 2005

2005-01-14T17:22:53Z

New page

[[Category:CP1610]]
<table border>
<tr><td>Instruction Name</td><td>Shift Logical Right</td></tr>
<tr><td>Mnemonic</td><td>SLR</td></tr>
<tr><td>CP1610 Clock Cycles</td><td>6 or 8</td></tr>
<tr><td>Interruptible</td><td>No</td></tr>
<tr><td>Opcode Range</td><td>$0060-$0067</td></tr>
<tr><td>Input Flags</td><td>None</td></tr>
<tr><td>Output Flags</td><td>[[Sign Flag]], [[Zero Flag]]</td></tr>
</table><br/>
The Shift Logical Right (SLR) instruction shifts the bits in the specified register either one (1) or two (2) bits to the right, stores the result back to the specified register, and sets or clears the [[Sign Flag]] and [[Zero Flag]] according to the new value in the register. The rightmost one or two bits are discarded and the leftmost one or two bits are set to zero(0). The number of clock cycles used depends on the number of shifts specified. One shift will use 6 clock cycles and two shifts will use 8 clock cycles. The opcode format is as follows.<br/>

0000:0000:0110:0srr<br/>
where:
s indicates the number of places to shift
such that:
s == 0 indicates to shift once
s == 1 indicates to shift twice<br/>
rr indicates the target register
such that:
rrr == 000 indicates register R0
rrr == 001 indicates register R1
rrr == 010 indicates register R2
rrr == 011 indicates register R3

← Older revision	Revision as of 09:12, 4 December 2010
(No difference)

@@ Line 9: / Line 9: @@
 <tr><td>Output Flags</td><td>[[Sign Flag]], [[Zero Flag]]</td></tr>
 </table><br/>
-The Shift Logical Right (SLR) instruction shifts the bits in the specified register either one (1) or two (2) bits to the right, stores the result back to the specified register, and sets or clears the [[Sign Flag]] and [[Zero Flag]] according to the new value in the register.  The rightmost one or two bits are discarded and the leftmost one or two bits are set to zero(0).  The number of clock cycles used depends on the number of shifts specified.  One shift will use 6 clock cycles and two shifts will use 8 clock cycles.  The opcode format is as follows.<br/>
+The Shift Logical Right (SLR) instruction shifts the bits in the specified register either one (1) or two (2) bits to the right, stores the result back to the specified register, and sets or clears the [[Sign Flag]] and [[Zero Flag]] according to the new value in the register.  The rightmost one or two bits are discarded and the leftmost one or two bits are set to zero(0).  The number of clock cycles used depends on the number of shifts specified.  One shift will use 6 clock cycles and two shifts will use 8 clock cycles.<br/><br/>
 :0000:0110:0srr<br/>

@@ Line 19: / Line 19: @@
          rr  indicates the target register
              such that:
-                 rrr == 000   indicates register R0
+                 rr == 00   indicates register R0
-                 rrr == 001   indicates register R1
+                 rr == 01   indicates register R1
-                 rrr == 010   indicates register R2
+                 rr == 10   indicates register R2
-                 rrr == 011   indicates register R3
+                 rr == 11   indicates register R3