SLLC - Revision history

Mr z: Protected "SLLC" ([edit=autoconfirmed] (indefinite) [move=autoconfirmed] (indefinite))

2010-12-04T09:12:04Z

Protected "SLLC" ([edit=autoconfirmed] (indefinite) [move=autoconfirmed] (indefinite))

Mr z at 14:57, 8 October 2007

2007-10-08T14:57:19Z

Pingaso at 17:37, 14 January 2005

2005-01-14T17:37:20Z

Pingaso at 17:27, 14 January 2005

2005-01-14T17:27:15Z

New page

[[Category:CP1610]]
<table border>
<tr><td>Instruction Name</td><td>Shift Logical Left Through Carry</td></tr>
<tr><td>Mnemonic</td><td>SLLC</td></tr>
<tr><td>CP1610 Clock Cycles</td><td>6 or 8</td></tr>
<tr><td>Interruptible</td><td>No</td></tr>
<tr><td>Opcode Range</td><td>$0058-$005F</td></tr>
<tr><td>Input Flags</td><td>None</td></tr>
<tr><td>Output Flags</td><td>[[Sign Flag]], [[Zero Flag]]</td></tr>
</table><br/>
The Shift Logical Left Through Carry (SLLC) instruction shifts the bits in the specified register by either one (1) or two (2) bits to the left, stores the result back to the specified register, and sets or clears the [[Sign Flag]] and [[Zero Flag]] according to the new value in the register. For either a single or double shift, the [[Carry Flag]] is set to the value of bit 15 before the shift occurred. For a double shift, the [[Overflow Flag]] is also set to the value of bit 14 before the shift occurred. The rightmost one or two bits are set to zero(0). The number of clock cycles used depends on the number of shifts specified. One shift will use 6 clock cycles and two shifts will use 8 clock cycles. The opcode format is as follows.<br/>

0000:0000:0101:1srr<br/>
where:
s indicates the number of places to shift
such that:
s == 0 indicates to shift once
s == 1 indicates to shift twice<br/>
rr indicates the target register
such that:
rrr == 000 indicates register R0
rrr == 001 indicates register R1
rrr == 010 indicates register R2
rrr == 011 indicates register R3

← Older revision	Revision as of 09:12, 4 December 2010
(No difference)

@@ Line 9: / Line 9: @@
 <tr><td>Output Flags</td><td>[[Sign Flag]], [[Zero Flag]], [[Overflow Flag]], [[Carry Flag]]</td></tr>
 </table><br/>
-The Shift Logical Left Through Carry (SLLC) instruction shifts the bits in the specified register by either one (1) or two (2) bits to the left, stores the result back to the specified register, and sets or clears the [[Sign Flag]] and [[Zero Flag]] according to the new value in the register.  For either a single or double shift, the [[Carry Flag]] is set to the value of bit 15 before the shift occurred.  For a double shift, the [[Overflow Flag]] is also set to the value of bit 14 before the shift occurred.  The rightmost one or two bits are set to zero(0).  The number of clock cycles used depends on the number of shifts specified.  One shift will use 6 clock cycles and two shifts will use 8 clock cycles.  The opcode format is as follows.<br/>
+The Shift Logical Left Through Carry (SLLC) instruction shifts the bits in the specified register by either one (1) or two (2) bits to the left, stores the result back to the specified register, and sets or clears the [[Sign Flag]] and [[Zero Flag]] according to the new value in the register.  For either a single or double shift, the [[Carry Flag]] is set to the value of bit 15 before the shift occurred.  For a double shift, the [[Overflow Flag]] is also set to the value of bit 14 before the shift occurred.  The rightmost one or two bits are set to zero(0).  The number of clock cycles used depends on the number of shifts specified.  One shift will use 6 clock cycles and two shifts will use 8 clock cycles.
 :0000:0101:1srr<br/>

@@ Line 7: / Line 7: @@
 <tr><td>Opcode Range</td><td>$0058-$005F</td></tr>
 <tr><td>Input Flags</td><td>None</td></tr>
-<tr><td>Output Flags</td><td>[[Sign Flag]], [[Zero Flag]]</td></tr>
+<tr><td>Output Flags</td><td>[[Sign Flag]], [[Zero Flag]], [[Overflow Flag]], [[Carry Flag]]</td></tr>
 </table><br/>
 The Shift Logical Left Through Carry (SLLC) instruction shifts the bits in the specified register by either one (1) or two (2) bits to the left, stores the result back to the specified register, and sets or clears the [[Sign Flag]] and [[Zero Flag]] according to the new value in the register.  For either a single or double shift, the [[Carry Flag]] is set to the value of bit 15 before the shift occurred.  For a double shift, the [[Overflow Flag]] is also set to the value of bit 14 before the shift occurred.  The rightmost one or two bits are set to zero(0).  The number of clock cycles used depends on the number of shifts specified.  One shift will use 6 clock cycles and two shifts will use 8 clock cycles.  The opcode format is as follows.<br/>