SAR - Revision history

Mr z: Protected "SAR" ([edit=autoconfirmed] (indefinite) [move=autoconfirmed] (indefinite))

2010-12-04T09:11:39Z

Protected "SAR" ([edit=autoconfirmed] (indefinite) [move=autoconfirmed] (indefinite))

Mr z at 14:55, 8 October 2007

2007-10-08T14:55:30Z

Arnauld at 00:12, 15 January 2005

2005-01-15T00:12:19Z

Pingaso at 17:39, 14 January 2005

2005-01-14T17:39:03Z

Pingaso at 17:34, 14 January 2005

2005-01-14T17:34:26Z

New page

[[Category:CP1610]]
<table border>
<tr><td>Instruction Name</td><td>Shift Arithmetic Right</td></tr>
<tr><td>Mnemonic</td><td>SAR</td></tr>
<tr><td>CP1610 Clock Cycles</td><td>6 or 8</td></tr>
<tr><td>Interruptible</td><td>No</td></tr>
<tr><td>Opcode Range</td><td>$0068-$006F</td></tr>
<tr><td>Input Flags</td><td>None</td></tr>
<tr><td>Output Flags</td><td>[[Sign Flag]], [[Zero Flag]]</td></tr>
</table><br/>
The Shift Arithmetic Right (SAR) instruction shifts the bits in the specified register either one (1) or two (2) bits to the right, stores the result back to the specified register, and sets or clears the [[Sign Flag]] and [[Zero Flag]] according to the new value in the register. The rightmost one or two bits are discarded. Unlike the [[Shift Logical Right]] instruction, however, the SLR instruction does not set the leftmost one or two bits to zero. Instead the value of bit 15 (the sign bit) stays the same value as the value of bit 15 before the shift occurred. For a double shift, bit 15 is also copied to bit 14. The number of clock cycles used depends on the number of shifts specified. One shift will use 6 clock cycles and two shifts will use 8 clock cycles. The opcode format is as follows.<br/>

0000:0000:0110:1srr<br/>
where:
s indicates the number of places to shift
such that:
s == 0 indicates to shift once
s == 1 indicates to shift twice<br/>
rr indicates the target register
such that:
rrr == 000 indicates register R0
rrr == 001 indicates register R1
rrr == 010 indicates register R2
rrr == 011 indicates register R3

← Older revision	Revision as of 09:11, 4 December 2010
(No difference)

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 <tr><td>Output Flags</td><td>[[Sign Flag]], [[Zero Flag]]</td></tr>
 </table><br/>
-The Shift Arithmetic Right (SAR) instruction shifts the bits in the specified register either one (1) or two (2) bits to the right, stores the result back to the specified register, and sets or clears the [[Sign Flag]] and [[Zero Flag]] according to the new value in the register.  The rightmost one or two bits are discarded.  Unlike the [[SLR|Shift Logical Right]] instruction, however, the SAR instruction does not set the leftmost one or two bits to zero.  Instead the value of bit 15 (the sign bit) stays the same value as the value of bit 15 before the shift occurred.  For a double shift, bit 15 is also copied to bit 14.  The number of clock cycles used depends on the number of shifts specified.  One shift will use 6 clock cycles and two shifts will use 8 clock cycles.  The opcode format is as follows.<br/>
+The Shift Arithmetic Right (SAR) instruction shifts the bits in the specified register either one (1) or two (2) bits to the right, stores the result back to the specified register, and sets or clears the [[Sign Flag]] and [[Zero Flag]] according to the new value in the register.  The rightmost one or two bits are discarded.  Unlike the [[SLR|Shift Logical Right]] instruction, however, the SAR instruction does not set the leftmost one or two bits to zero.  Instead the value of bit 15 (the sign bit) stays the same value as the value of bit 15 before the shift occurred.  For a double shift, bit 15 is also copied to bit 14.  The number of clock cycles used depends on the number of shifts specified.  One shift will use 6 clock cycles and two shifts will use 8 clock cycles.<br/><br/>
 :0000:0110:1srr<br/>