RLC - Revision history

Mr z: Protected "RLC" ([edit=autoconfirmed] (indefinite) [move=autoconfirmed] (indefinite))

2010-12-04T09:08:42Z

Protected "RLC" ([edit=autoconfirmed] (indefinite) [move=autoconfirmed] (indefinite))

Mr z at 14:53, 8 October 2007

2007-10-08T14:53:52Z

Arnauld at 23:30, 14 January 2005

2005-01-14T23:30:06Z

Pingaso at 17:55, 14 January 2005

2005-01-14T17:55:06Z

Pingaso at 17:52, 14 January 2005

2005-01-14T17:52:53Z

New page

[[Category:CP1610]]
<table border>
<tr><td>Instruction Name</td><td>Rotate Left Through Carry</td></tr>
<tr><td>Mnemonic</td><td>RLC</td></tr>
<tr><td>CP1610 Clock Cycles</td><td>6 or 8</td></tr>
<tr><td>Interruptible</td><td>No</td></tr>
<tr><td>Opcode Range</td><td>$0050-$0057</td></tr>
<tr><td>Input Flags</td><td>[[Overflow Flag]], [[Carry Flag]]</td></tr>
<tr><td>Output Flags</td><td>[[Sign Flag]], [[Zero Flag]], [[Overflow Flag]], [[Carry Flag]]</td></tr>
</table><br/>
The Rotae Left Through Carry (RLC) instruction rotates the bits in the specified register by one or two bits. For a single rotate, the [[Carry Flag]] is set to the value of bit 15, the value is shifted to the left by one bit, and bit 0 becomes the previous value of the [[Carry Flag]]. For a double rotate, the [[Carry Flag]] is set to the value of bit 15, the [[Overflow Flag]] is set to the value of bit 14, the value is shifted to the left by two bits, bit 1 becomes the previous value of the [[Carry Flag]], and bit 0 becomes the previous value of the [[Overflow Flag]]. The resulting value is stored back to the specified register, and the [[Sign Flag]] and [[Zero Flag]] are set or cleared according to the new value in the register. The number of clock cycles used depends on the number of shifts specified. One shift will use 6 clock cycles and two shifts will use 8 clock cycles. The opcode format is as follows.<br/>

0000:0000:0100:1srr<br/>
where:
s indicates the number of places to rotate
such that:
s == 0 indicates to rotate once
s == 1 indicates to rotate twice<br/>
rr indicates the target register
such that:
rrr == 000 indicates register R0
rrr == 001 indicates register R1
rrr == 010 indicates register R2
rrr == 011 indicates register R3

@@ Line 9: / Line 9: @@
 <tr><td>Output Flags</td><td>[[Sign Flag]], [[Zero Flag]], [[Overflow Flag]], [[Carry Flag]]</td></tr>
 </table><br/>
-The Rotate Left Through Carry (RLC) instruction rotates the bits in the specified register by one or two bits.  For a single rotate, the [[Carry Flag]] is set to the value of bit 15, the value is shifted to the left by one bit, and bit 0 becomes the previous value of the [[Carry Flag]].  For a double rotate, the [[Carry Flag]] is set to the value of bit 15, the [[Overflow Flag]] is set to the value of bit 14, the value is shifted to the left by two bits, bit 1 becomes the previous value of the [[Carry Flag]], and bit 0 becomes the previous value of the [[Overflow Flag]].  The resulting value is stored back to the specified register, and the [[Sign Flag]] and [[Zero Flag]] are set or cleared according to the new value in the register.  The number of clock cycles used depends on the number of shifts specified.  A single rotate will use 6 clock cycles and a double rotate will use 8 clock cycles.  The opcode format is as follows.<br/>
+The Rotate Left Through Carry (RLC) instruction rotates the bits in the specified register by one or two bits.  For a single rotate, the [[Carry Flag]] is set to the value of bit 15, the value is shifted to the left by one bit, and bit 0 becomes the previous value of the [[Carry Flag]].  For a double rotate, the [[Carry Flag]] is set to the value of bit 15, the [[Overflow Flag]] is set to the value of bit 14, the value is shifted to the left by two bits, bit 1 becomes the previous value of the [[Carry Flag]], and bit 0 becomes the previous value of the [[Overflow Flag]].  The resulting value is stored back to the specified register, and the [[Sign Flag]] and [[Zero Flag]] are set or cleared according to the new value in the register.  The number of clock cycles used depends on the number of shifts specified.  A single rotate will use 6 clock cycles and a double rotate will use 8 clock cycles.<br/><br/>
 :0000:0101:1srr<br/>

@@ Line 9: / Line 9: @@
 <tr><td>Output Flags</td><td>[[Sign Flag]], [[Zero Flag]], [[Overflow Flag]], [[Carry Flag]]</td></tr>
 </table><br/>
-The Rotae Left Through Carry (RLC) instruction rotates the bits in the specified register by one or two bits.  For a single rotate, the [[Carry Flag]] is set to the value of bit 15, the value is shifted to the left by one bit, and bit 0 becomes the previous value of the [[Carry Flag]].  For a double rotate, the [[Carry Flag]] is set to the value of bit 15, the [[Overflow Flag]] is set to the value of bit 14, the value is shifted to the left by two bits, bit 1 becomes the previous value of the [[Carry Flag]], and bit 0 becomes the previous value of the [[Overflow Flag]].  The resulting value is stored back to the specified register, and the [[Sign Flag]] and [[Zero Flag]] are set or cleared according to the new value in the register.  The number of clock cycles used depends on the number of shifts specified.  A single rotate will use 6 clock cycles and a double rotate will use 8 clock cycles.  The opcode format is as follows.<br/>
+The Rotate Left Through Carry (RLC) instruction rotates the bits in the specified register by one or two bits.  For a single rotate, the [[Carry Flag]] is set to the value of bit 15, the value is shifted to the left by one bit, and bit 0 becomes the previous value of the [[Carry Flag]].  For a double rotate, the [[Carry Flag]] is set to the value of bit 15, the [[Overflow Flag]] is set to the value of bit 14, the value is shifted to the left by two bits, bit 1 becomes the previous value of the [[Carry Flag]], and bit 0 becomes the previous value of the [[Overflow Flag]].  The resulting value is stored back to the specified register, and the [[Sign Flag]] and [[Zero Flag]] are set or cleared according to the new value in the register.  The number of clock cycles used depends on the number of shifts specified.  A single rotate will use 6 clock cycles and a double rotate will use 8 clock cycles.  The opcode format is as follows.<br/>
 :0000:0101:1srr<br/>

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