MVII - Revision history

Mr z: Protected "MVII" ([edit=autoconfirmed] (indefinite) [move=autoconfirmed] (indefinite))

2010-12-04T08:54:13Z

Protected "MVII" ([edit=autoconfirmed] (indefinite) [move=autoconfirmed] (indefinite))

Pingaso at 16:42, 17 January 2005

2005-01-17T16:42:13Z

Pingaso at 16:39, 17 January 2005

2005-01-17T16:39:05Z

New page

[[Category:CP1610]]
<table border>
<tr><td>Instruction Name</td><td>Move In Indirect</td></tr>
<tr><td>Mnemonic</td><td>MVI@</td></tr>
<tr><td>CP1610 Clock Cycles</td><td>8, 10, or 11</td></tr>
<tr><td>Interruptible</td><td>Yes</td></tr>
<tr><td>Opcode Range</td><td>$0288-$02Bf</td></tr>
<tr><td>Input Flags</td><td>[[Double Byte Data Flag]]</td></tr>
<tr><td>Output Flags</td><td>None</td></tr>
</table> 
The Move In Indirect (MVI@) instruction copies the value from the address contained in the specified address register into the specified destination register. Assuming the [[Double Byte Data Flag]] is clear, then this instruction will use 8 clock cycles unless R6 is used as the address register, in which case it will use 11 clock cycles. 

If the [[Double Byte Data Flag]] is set, then this instruction will perform two indirect reads, using the lowest 8 bits of the first read as the lowest 8 bits of the resulting value and combining them with the lowest 8 bits of the second read as the highest 8 bits of the resulting value. Note that if the address register is R0-R3 (which do not auto-increment or auto-decrement), then the register value will not change between successive indirect reads, and thus the same value at the same address would be read for both indirect reads. If the [[Double Byte Data Flag]] is set, this instruction will always use exactly 10 clock cycles regardless of which register is used as the address register. 

0000:0010:10aa:addd 
where:
ddd indicates the register containing the value to move
such that:
ddd == 000 indicates register R0
ddd == 001 indicates register R1
ddd == 010 indicates register R2
ddd == 011 indicates register R3
ddd == 100 indicates register R4
ddd == 101 indicates register R5
ddd == 110 indicates register R6
ddd == 111 indicates register R7 
aaa indicates the register containing the address
such that:
aaa == 000 indicates register R0
aaa == 001 indicates register R1
aaa == 010 indicates register R2
aaa == 011 indicates register R3
aaa == 100 indicates register R4
aaa == 101 indicates register R5
aaa == 110 indicates register R6
aaa == 111 indicates register R7

← Older revision	Revision as of 08:54, 4 December 2010
(No difference)

@@ Line 1: / Line 1: @@
 [[Category:CP1610]]
 <table border>
-<tr><td>Instruction Name</td><td>Move In Indirect</td></tr>
+<tr><td>Instruction Name</td><td>Move In Immediate</td></tr>
-<tr><td>Mnemonic</td><td>MVI@</td></tr>
+<tr><td>Mnemonic</td><td>MVII</td></tr>
-<tr><td>CP1610 Clock Cycles</td><td>8, 10, or 11</td></tr>
+<tr><td>CP1610 Clock Cycles</td><td>8, 10</td></tr>
 <tr><td>Interruptible</td><td>Yes</td></tr>
-<tr><td>Opcode Range</td><td>$0288-$02Bf</td></tr>
+<tr><td>Opcode Range</td><td>$02B0-$02BF</td></tr>
 <tr><td>Input Flags</td><td>[[Double Byte Data Flag]]</td></tr>
 <tr><td>Output Flags</td><td>None</td></tr>
 </table><br/>
-The Move In Indirect (MVI@) instruction copies the value from the address contained in the specified address register into the specified destination register.  Assuming the [[Double Byte Data Flag]] is <strong>clear</strong>, then this instruction will use 8 clock cycles <strong>unless</strong> R6 is used as the address register, in which case it will use 11 clock cycles.<br/><br/>
+The Move In Immediate (MVII) instruction copies the value at the address immediately following the opcode to the specified destination register.  Note that this instruction is really just a variant of the [[MVI@|Move In Indirect]] instruction using R7 as the address register.  See the [[MVI@|Move In Indirect]] documentation for more information.<br/>
-If the [[Double Byte Data Flag]] is set, then this instruction will perform two indirect reads, using the lowest 8 bits of the first read as the lowest 8 bits of the resulting value and combining them with the lowest 8 bits of the second read as the highest 8 bits of the resulting value. Note that if the address register is R0-R3 (which do <strong>not</strong> auto-increment or auto-decrement), then the register value will not change between successive indirect reads, and thus the same value at the same address would be read for both indirect reads.  If the [[Double Byte Data Flag]] is set, this instruction will always use exactly 10 clock cycles regardless of which register is used as the address register.<br/>
+:0010:1011:1ddd<br/>
      where:
-         ddd   indicates the register containing the value to move
+         ddd   indicates the destination register
                such that:
                    ddd == 000    indicates register R0
@@ Line 25: / Line 23: @@
                    ddd == 110    indicates register R6
                    ddd == 111    indicates register R7<br/>