MVI@ - Revision history

Mr z: Protected "MVI@" ([edit=autoconfirmed] (indefinite) [move=autoconfirmed] (indefinite))

2010-12-04T08:52:57Z

Protected "MVI@" ([edit=autoconfirmed] (indefinite) [move=autoconfirmed] (indefinite))

Mr z at 16:27, 7 November 2007

2007-11-07T16:27:47Z

Mr z at 16:26, 7 November 2007

2007-11-07T16:26:29Z

Mr z at 21:54, 7 October 2007

2007-10-07T21:54:51Z

Mr z at 21:52, 7 October 2007

2007-10-07T21:52:34Z

Mr z at 21:47, 7 October 2007

2007-10-07T21:47:02Z

Mr z at 21:40, 7 October 2007

2007-10-07T21:40:28Z

Mr z at 21:37, 7 October 2007

2007-10-07T21:37:36Z

Pingaso at 16:42, 17 January 2005

2005-01-17T16:42:49Z

Pingaso at 20:26, 12 January 2005

2005-01-12T20:26:06Z

New page

[[Category:CP1610]]
<table border>
<tr><td>Instruction Name</td><td>Move In Indirect</td></tr>
<tr><td>Mnemonic</td><td>MVI@</td></tr>
<tr><td>CP1610 Clock Cycles</td><td>8, 10, or 11</td></tr>
<tr><td>Interruptible</td><td>Yes</td></tr>
<tr><td>Opcode Range</td><td>$0288-$02Bf</td></tr>
<tr><td>Input Flags</td><td>[[Double Byte Data Flag]]</td></tr>
<tr><td>Output Flags</td><td>None</td></tr>
</table> 
The Move In Indirect (MVI@) instruction copies the value from the address contained in the specified address register into the specified destination register. Assuming the [[Double Byte Data Flag]] is clear, then this instruction will use 8 clock cycles unless R6 is used as the address register, in which case it will use 11 clock cycles. 

If the [[Double Byte Data Flag]] is set, then this instruction will perform two indirect reads, using the lowest 8 bits of the first read as the lowest 8 bits of the resulting value and combining them with the lowest 8 bits of the second read as the highest 8 bits of the resulting value. Note that if the address register is R0-R3 (which do not auto-increment or auto-decrement), then the register value will not change between successive indirect reads, and thus the same value at the same address would be read for both indirect reads. If the [[Double Byte Data Flag]] is set, this instruction will always use exactly 10 clock cycles regardless of which register is used as the address register. 

0000:0010:10aa:addd 
where:
ddd indicates the register containing the value to move
such that:
ddd == 000 indicates register R0
ddd == 001 indicates register R1
ddd == 010 indicates register R2
ddd == 011 indicates register R3
ddd == 100 indicates register R4
ddd == 101 indicates register R5
ddd == 110 indicates register R6
ddd == 111 indicates register R7 
aaa indicates the register containing the address
such that:
aaa == 000 indicates register R0
aaa == 001 indicates register R1
aaa == 010 indicates register R2
aaa == 011 indicates register R3
aaa == 100 indicates register R4
aaa == 101 indicates register R5
aaa == 110 indicates register R6
aaa == 111 indicates register R7

@@ Line 11: / Line 11: @@
 The Move In Indirect (MVI@) instruction copies the value from the address contained in the specified address register into the specified destination register.  Assuming the [[Double Byte Data Flag]] is <strong>clear</strong>, then this instruction will use 8 clock cycles <strong>unless</strong> R6 is used as the address register, in which case it will use 11 clock cycles.<br/><br/>
-If prefixed with [[SDBD]], this instruction will perform two indirect reads to build a 16-bit value, and will always use exactly 10 clock cycles regardless of which register is used as the address register.  See [[Double Byte Data]] for more details on how [[SDBD]] interacts with [[Indirect Mode]].<br/><br/>
+If prefixed with [[SDBD]], this instruction will perform two indirect reads to build a 16-bit value for its first operand, and will always use exactly 10 clock cycles regardless of which register is used as the address register.  See [[Double Byte Data]] for more details on how [[SDBD]] interacts with [[Indirect Mode]].<br/><br/>
 The "PULR Rx" instruction is an alias for "MVI@ R6, Rx".

@@ Line 11: / Line 11: @@
 The Move In Indirect (MVI@) instruction copies the value from the address contained in the specified address register into the specified destination register.  Assuming the [[Double Byte Data Flag]] is <strong>clear</strong>, then this instruction will use 8 clock cycles <strong>unless</strong> R6 is used as the address register, in which case it will use 11 clock cycles.<br/><br/>
-If the [[Double Byte Data Flag]] is set, then this instruction will perform two indirect reads, using the lowest 8 bits of the first read as the lowest 8 bits of the resulting value and combining them with the lowest 8 bits of the second read as the highest 8 bits of the resulting value. Note that if the address register is R0-R3 (which do <strong>not</strong> auto-increment or auto-decrement), then the register value will not change between successive indirect reads, and thus the same value at the same address would be read for both indirect reads.  If the [[Double Byte Data Flag]] is set, this instruction will always use exactly 10 clock cycles regardless of which register is used as the address register.<br/><br/>
+If prefixed with [[SDBD]], this instruction will perform two indirect reads to build a 16-bit value, and will always use exactly 10 clock cycles regardless of which register is used as the address register.  See [[Double Byte Data]] for more details on how [[SDBD]] interacts with [[Indirect Mode]].<br/><br/>
 The "PULR Rx" instruction is an alias for "MVI@ R6, Rx".

@@ Line 11: / Line 11: @@
 The Move In Indirect (MVI@) instruction copies the value from the address contained in the specified address register into the specified destination register.  Assuming the [[Double Byte Data Flag]] is <strong>clear</strong>, then this instruction will use 8 clock cycles <strong>unless</strong> R6 is used as the address register, in which case it will use 11 clock cycles.<br/><br/>
-If the [[Double Byte Data Flag]] is set, then this instruction will perform two indirect reads, using the lowest 8 bits of the first read as the lowest 8 bits of the resulting value and combining them with the lowest 8 bits of the second read as the highest 8 bits of the resulting value. Note that if the address register is R0-R3 (which do <strong>not</strong> auto-increment or auto-decrement), then the register value will not change between successive indirect reads, and thus the same value at the same address would be read for both indirect reads.  If the [[Double Byte Data Flag]] is set, this instruction will always use exactly 10 clock cycles regardless of which register is used as the address register.<br/>
+If the [[Double Byte Data Flag]] is set, then this instruction will perform two indirect reads, using the lowest 8 bits of the first read as the lowest 8 bits of the resulting value and combining them with the lowest 8 bits of the second read as the highest 8 bits of the resulting value. Note that if the address register is R0-R3 (which do <strong>not</strong> auto-increment or auto-decrement), then the register value will not change between successive indirect reads, and thus the same value at the same address would be read for both indirect reads.  If the [[Double Byte Data Flag]] is set, this instruction will always use exactly 10 clock cycles regardless of which register is used as the address register.<br/><br/>
 The "PULR Rx" instruction is an alias for "MVI@ R6, Rx".

← Older revision		Revision as of 21:52, 7 October 2007
Line 12:		Line 12:

	If the [[Double Byte Data Flag]] is set, then this instruction will perform two indirect reads, using the lowest 8 bits of the first read as the lowest 8 bits of the resulting value and combining them with the lowest 8 bits of the second read as the highest 8 bits of the resulting value. Note that if the address register is R0-R3 (which do <strong>not</strong> auto-increment or auto-decrement), then the register value will not change between successive indirect reads, and thus the same value at the same address would be read for both indirect reads. If the [[Double Byte Data Flag]] is set, this instruction will always use exactly 10 clock cycles regardless of which register is used as the address register.<br/>		If the [[Double Byte Data Flag]] is set, then this instruction will perform two indirect reads, using the lowest 8 bits of the first read as the lowest 8 bits of the resulting value and combining them with the lowest 8 bits of the second read as the highest 8 bits of the resulting value. Note that if the address register is R0-R3 (which do <strong>not</strong> auto-increment or auto-decrement), then the register value will not change between successive indirect reads, and thus the same value at the same address would be read for both indirect reads. If the [[Double Byte Data Flag]] is set, this instruction will always use exactly 10 clock cycles regardless of which register is used as the address register.<br/>
		+
		+	The "PULR Rx" instruction is an alias for "MVI@ R6, Rx".

	0000:0010:10aa:addd<br/>		0000:0010:10aa:addd<br/>

← Older revision	Revision as of 08:52, 4 December 2010
(No difference)

@@ Line 33: / Line 33: @@
                    aaa == 100    indicates register R4
                    aaa == 101    indicates register R5
-                   aaa == 110    indicates register R6
+                   aaa == 110    indicates register R6, which operates in [[Stack Mode|stack mode]]
                    aaa == 111    indicates register R7, alias for [[Immediate Mode|immediate mode]] [[MVII]]<br/>

@@ Line 27: / Line 27: @@
          aaa   indicates the register containing the address
                such that:
-                   aaa == 000    not allowed (aliases "direct mode" encoding)
+                   aaa == 000    indicates [[Direct Mode|direct mode]] [[MVI]] instruction
                    aaa == 001    indicates register R1
                    aaa == 010    indicates register R2
@@ Line 34: / Line 34: @@
                    aaa == 101    indicates register R5
                    aaa == 110    indicates register R6
-                   aaa == 111    indicates register R7 (equivalent to "immediate mode")<br/>
+                   aaa == 111    indicates register R7, alias for [[Immediate Mode|immediate mode]] [[MVII]]<br/>

@@ Line 5: / Line 5: @@
 <tr><td>CP1610 Clock Cycles</td><td>8, 10, or 11</td></tr>
 <tr><td>Interruptible</td><td>Yes</td></tr>
-<tr><td>Opcode Range</td><td>$0288-$02Bf</td></tr>
+<tr><td>Opcode Range</td><td>$0288-$02AF</td></tr>
 <tr><td>Input Flags</td><td>[[Double Byte Data Flag]]</td></tr>
 <tr><td>Output Flags</td><td>None</td></tr>