Bus Copy - Revision history

Mr z: Protected "Bus Copy" ([edit=autoconfirmed] (indefinite) [move=autoconfirmed] (indefinite))

2010-12-04T08:08:21Z

Protected "Bus Copy" ([edit=autoconfirmed] (indefinite) [move=autoconfirmed] (indefinite))

Arnauld at 01:13, 2 February 2005

2005-02-02T01:13:25Z

Mr z at 01:25, 12 January 2005

2005-01-12T01:25:47Z

Mr z at 01:25, 12 January 2005

2005-01-12T01:25:33Z

Pingaso at 22:15, 11 January 2005

2005-01-11T22:15:48Z

Pingaso at 22:15, 11 January 2005

2005-01-11T22:15:33Z

Mr z: /* retarget BUSAK to STIC Bus Request */

2005-01-11T09:12:42Z

‎retarget BUSAK to STIC Bus Request

Mr z: /* wording improvement */

2005-01-11T07:54:47Z

‎wording improvement

Mr z: /* explain the $21 RW alias conundrum */

2005-01-11T07:48:02Z

‎explain the $21 RW alias conundrum

Mr z: /* explain the origin of STIC/GRAM/GROM aliases */

2005-01-11T07:42:08Z

‎explain the origin of STIC/GRAM/GROM aliases

@@ Line 1: / Line 1: @@
 [[Category:STIC]][[Category:CP1610]]
-The [[System RAM]] serves as a bridge between the CPU's main busses and the STIC's private graphics bus.  At the start the [[VBlank Interval]] (or more correctly, when the System RAM sees the CPU issue "INTAK" in response to the STIC's [[VBlank Interrupt]]), the System RAM enters Bus Copy mode.  This allows the CPU access to the [[STIC]]'s registers, as well as the [[Graphics RAM|GRAM]] and [[Graphics ROM|GROM]].  The System RAM exits Bus Copy mode when it sees a [[STIC Bus Request|BUSAK]] signal from the CP-1610 CPU.  This usually occurs just before the STIC starts active display at the end of [[VBlank Period 2]].
+The [[System RAM]] serves as a bridge between the CPU's main busses and the STIC's private graphics bus.  At the start of the [[VBlank Interval]] (or more correctly, when the System RAM sees the CPU issue "INTAK" in response to the STIC's [[VBlank Interrupt]]), the System RAM enters Bus Copy mode.  This allows the CPU access to the [[STIC]]'s registers, as well as the [[Graphics RAM|GRAM]] and [[Graphics ROM|GROM]].  The System RAM exits Bus Copy mode when it sees a [[STIC Bus Request|BUSAK]] signal from the CP-1610 CPU.  This usually occurs just before the STIC starts active display at the end of [[VBlank Period 2]].
 Bus Copy mode is a very simple mode in which the System RAM simply copies all values on the CPU's address and data bus to the STIC's graphics bus.  The System RAM reverses the direction of the copy only when the address currently being accessed is in the range $0000-$007F or $3000-$3FFF, and the current [[Bus Phases|Bus Phase]] is DTB (Data To Bus).  (It <I>may</I> also reverse the direction during the ADAR bus phase, but it appears System RAM treats ADAR the same as BAR.)  The System RAM does not copy the bus phase through to the STIC, GRAM and GROM.  Rather, the STIC looks directly at the bus phase, and decodes it on behalf of the GRAM and GROM.

@@ Line 2: / Line 2: @@
 The [[System RAM]] serves as a bridge between the CPU's main busses and the STIC's private graphics bus.  At the start the [[VBlank Interval]] (or more correctly, when the System RAM sees the CPU issue "INTAK" in response to the STIC's [[VBlank Interrupt]]), the System RAM enters Bus Copy mode.  This allows the CPU access to the [[STIC]]'s registers, as well as the [[Graphics RAM|GRAM]] and [[Graphics ROM|GROM]].  The System RAM exits Bus Copy mode when it sees a [[STIC Bus Request|BUSAK]] signal from the CP-1610 CPU.  This usually occurs just before the STIC starts active display at the end of [[VBlank Period 2]].
-Bus Copy mode is a very simple mode in which the System RAM simply copies all values on the CPU's address and data bus to the STIC's graphics bus.  The System RAM reverses the direction of the copy only when the address currently being accessed is in the range $0000-$007F or $3000-$3FFF, and the current [[Bus Phase]] is DTB (Data To Bus).  (It <I>may</I> also reverse the direction during the ADAR bus phase, but it appears System RAM treats ADAR the same as BAR.)  The System RAM does not copy the bus phase through to the STIC, GRAM and GROM.  Rather, the STIC looks directly at the bus phase, and decodes it on behalf of the GRAM and GROM.
+Bus Copy mode is a very simple mode in which the System RAM simply copies all values on the CPU's address and data bus to the STIC's graphics bus.  The System RAM reverses the direction of the copy only when the address currently being accessed is in the range $0000-$007F or $3000-$3FFF, and the current [[Bus Phases|Bus Phase]] is DTB (Data To Bus).  (It <I>may</I> also reverse the direction during the ADAR bus phase, but it appears System RAM treats ADAR the same as BAR.)  The System RAM does not copy the bus phase through to the STIC, GRAM and GROM.  Rather, the STIC looks directly at the bus phase, and decodes it on behalf of the GRAM and GROM.
 The CPU's main address/data bus is 16 bits wide, whereas the STIC's graphics bus is only 14 bits wide.  The System RAM decodes all 16 bits, whereas the STIC cannot.  This leads to several interesting phenomena:

@@ Line 1: / Line 1: @@
 [[Category:STIC]][[Category:CP1610]]
-The [[System RAM]] serves as a bridge between the CPU's main busses and the STIC's private graphics bus.  During the [[VBlank Interval]], the System RAM enters Bus Copy mode to allow the CPU access to the [[STIC]]'s registers, as well as the [[Graphics RAM|GRAM]] and [[Graphics ROM|GROM]].  The System RAM exits Bus Copy mode when it sees a [[STIC Bus Request|BUSAK]] signal from the CP-1610 CPU.  This usually occurs just before the STIC starts active display at the end of [[VBlank Period 2]].
+The [[System RAM]] serves as a bridge between the CPU's main busses and the STIC's private graphics bus.  At the start the [[VBlank Interval]] (or more correctly, when the System RAM sees the CPU issue "INTAK" in response to the STIC's [[VBlank Interrupt]]), the System RAM enters Bus Copy mode.  This allows the CPU access to the [[STIC]]'s registers, as well as the [[Graphics RAM|GRAM]] and [[Graphics ROM|GROM]].  The System RAM exits Bus Copy mode when it sees a [[STIC Bus Request|BUSAK]] signal from the CP-1610 CPU.  This usually occurs just before the STIC starts active display at the end of [[VBlank Period 2]].
-The CPU's main address/data bus is 16 bits wide, whereas the STIC's graphics bus is only 14 bits wide.  This leads to several interesting phenomena:
+Bus Copy mode is a very simple mode in which the System RAM simply copies all values on the CPU's address and data bus to the STIC's graphics bus.  The System RAM reverses the direction of the copy only when the address currently being accessed is in the range $0000-$007F or $3000-$3FFF, and the current [[Bus Phase]] is DTB (Data To Bus).  (It <I>may</I> also reverse the direction during the ADAR bus phase, but it appears System RAM treats ADAR the same as BAR.)  The System RAM does not copy the bus phase through to the STIC, GRAM and GROM.  Rather, the STIC looks directly at the bus phase, and decodes it on behalf of the GRAM and GROM.
 * The STIC ignores upper 2 bits of each word in [[BACKTAB]].  Programs can (and do) use them as flag bits.
 * The STIC [[Incomplete_Address_Decoding|does not completely decode CPU addresses]], primarily because it can only see 14 of the 16 address bits.
@@ Line 8: / Line 10: @@
 ** If the address was in the range $4000 - $FFFF, the System RAM refuses to forward the STIC's responses to reads back to the CPU.  Thus, one cannot read the contents of GRAM, GROM or STIC registers at any of their aliases.
 ** System RAM always copies through writes, however, leading to several dubiously usable write-only aliases in the [[Memory Map]].
-** The STIC decodes bus phases separately from the System RAM.  Thus, programs can switch between Foreground/Background and Color Stack modes by accessing any one of location $21's aliases, since it's simply the access itself and not the data transfered that sets the mode.
+** Because STIC decodes bus phases directly, programs can switch between Foreground/Background and Color Stack modes by accessing any one of location $21's aliases, since it's simply the access itself and not the data transfered that sets the mode.

← Older revision		Revision as of 22:15, 11 January 2005
Line 1:		Line 1:
−	[[Category:STIC]]	+	[[Category:STIC]][[Category:CP1610]]
−	[[Category:CP1610]]
	The [[System RAM]] serves as a bridge between the CPU's main busses and the STIC's private graphics bus. During the [[VBlank Interval]], the System RAM enters Bus Copy mode to allow the CPU access to the [[STIC]]'s registers, as well as the [[Graphics RAM\|GRAM]] and [[Graphics ROM\|GROM]]. The System RAM exits Bus Copy mode when it sees a [[STIC Bus Request\|BUSAK]] signal from the CP-1610 CPU. This usually occurs just before the STIC starts active display at the end of [[VBlank Period 2]].		The [[System RAM]] serves as a bridge between the CPU's main busses and the STIC's private graphics bus. During the [[VBlank Interval]], the System RAM enters Bus Copy mode to allow the CPU access to the [[STIC]]'s registers, as well as the [[Graphics RAM\|GRAM]] and [[Graphics ROM\|GROM]]. The System RAM exits Bus Copy mode when it sees a [[STIC Bus Request\|BUSAK]] signal from the CP-1610 CPU. This usually occurs just before the STIC starts active display at the end of [[VBlank Period 2]].

← Older revision		Revision as of 22:15, 11 January 2005
Line 1:		Line 1:
		+	[[Category:STIC]]
		+	[[Category:CP1610]]
	The [[System RAM]] serves as a bridge between the CPU's main busses and the STIC's private graphics bus. During the [[VBlank Interval]], the System RAM enters Bus Copy mode to allow the CPU access to the [[STIC]]'s registers, as well as the [[Graphics RAM\|GRAM]] and [[Graphics ROM\|GROM]]. The System RAM exits Bus Copy mode when it sees a [[STIC Bus Request\|BUSAK]] signal from the CP-1610 CPU. This usually occurs just before the STIC starts active display at the end of [[VBlank Period 2]].		The [[System RAM]] serves as a bridge between the CPU's main busses and the STIC's private graphics bus. During the [[VBlank Interval]], the System RAM enters Bus Copy mode to allow the CPU access to the [[STIC]]'s registers, as well as the [[Graphics RAM\|GRAM]] and [[Graphics ROM\|GROM]]. The System RAM exits Bus Copy mode when it sees a [[STIC Bus Request\|BUSAK]] signal from the CP-1610 CPU. This usually occurs just before the STIC starts active display at the end of [[VBlank Period 2]].

← Older revision	Revision as of 08:08, 4 December 2010
(No difference)

← Older revision		Revision as of 09:12, 11 January 2005
Line 1:		Line 1:
−	The [[System RAM]] serves as a bridge between the CPU's main busses and the STIC's private graphics bus. During the [[VBlank Interval]], the System RAM enters Bus Copy mode to allow the CPU access to the [[STIC]]'s registers, as well as the [[Graphics RAM\|GRAM]] and [[Graphics ROM\|GROM]]. The System RAM exits Bus Copy mode when it sees a [[BUSAK]] signal from the CP-1610 CPU. This usually occurs just before the STIC starts active display at the end of [[VBlank Period 2]].	+	The [[System RAM]] serves as a bridge between the CPU's main busses and the STIC's private graphics bus. During the [[VBlank Interval]], the System RAM enters Bus Copy mode to allow the CPU access to the [[STIC]]'s registers, as well as the [[Graphics RAM\|GRAM]] and [[Graphics ROM\|GROM]]. The System RAM exits Bus Copy mode when it sees a [[STIC Bus Request\|BUSAK]] signal from the CP-1610 CPU. This usually occurs just before the STIC starts active display at the end of [[VBlank Period 2]].

	The CPU's main address/data bus is 16 bits wide, whereas the STIC's graphics bus is only 14 bits wide. This leads to several interesting phenomena:		The CPU's main address/data bus is 16 bits wide, whereas the STIC's graphics bus is only 14 bits wide. This leads to several interesting phenomena:

@@ Line 4: / Line 4: @@
 * The STIC ignores upper 2 bits of each word in [[BACKTAB]].  Programs can (and do) use them as flag bits.
 * The STIC [[Incomplete_Address_Decoding|does not completely decode CPU addresses]], primarily because it can only see 14 of the 16 address bits.
-* The System RAM <I>does</I> see the full 16 bit address, and so refuses to copy the STIC's responses to reads if the address was outside the first 16K of the address map:
+* The System RAM <I>does</I> see the full 16 bit address, leading to some oddities:
-** System RAM always copies through writes, leading to several usable write-only aliases in the [[Memory Map]].
+** If the address was in the range $4000 - $FFFF, the System RAM refuses to forward the STIC's responses to reads back to the CPU.  Thus, one cannot read the contents of GRAM, GROM or STIC registers at any of their aliases.
-** The STIC decodes bus phases separately from the System RAM, which is why the Mode Select register (at location $21) responds to both reads and writes at all its aliases, whereas the other registers <I>appear</I> to respond only to writes at their aliases.
+** System RAM always copies through writes, however, leading to several dubiously usable write-only aliases in the [[Memory Map]].

← Older revision		Revision as of 07:42, 11 January 2005
Line 1:		Line 1:
−	The [[System RAM]] serves as a bridge between the CPU's main busses and the STIC's private graphics bus. During the [[VBlank Interval]], the System RAM enters Bus Copy mode to allow the CPU access to the [[STIC]]'s registers, as well as the [[GRAM]] and [[GROM]]. The System RAM exits Bus Copy mode when it sees a [[BUSAK]] signal from the CP-1610 CPU. This usually occurs just before the STIC starts active display at the end of [[VBlank Period 2]].	+	The [[System RAM]] serves as a bridge between the CPU's main busses and the STIC's private graphics bus. During the [[VBlank Interval]], the System RAM enters Bus Copy mode to allow the CPU access to the [[STIC]]'s registers, as well as the [[Graphics RAM\|GRAM]] and [[Graphics ROM\|GROM]]. The System RAM exits Bus Copy mode when it sees a [[BUSAK]] signal from the CP-1610 CPU. This usually occurs just before the STIC starts active display at the end of [[VBlank Period 2]].
		+
		+	The CPU's main address/data bus is 16 bits wide, whereas the STIC's graphics bus is only 14 bits wide. This leads to several interesting phenomena:
		+	* The STIC ignores upper 2 bits of each word in [[BACKTAB]]. Programs can (and do) use them as flag bits.
		+	* The STIC [[Incomplete_Address_Decoding\|does not completely decode CPU addresses]], primarily because it can only see 14 of the 16 address bits.
		+	* The System RAM <I>does</I> see the full 16 bit address, and so refuses respond to reads outside the first 16K of the address map. But, it always copies through writes, leading to several write-only aliases in the [[Memory Map]].