ADD@ - Revision history

BrandonE: Fixed bit code.

2012-07-20T21:11:16Z

Fixed bit code.

Mr z: Protected "ADD@" ([edit=autoconfirmed] (indefinite) [move=autoconfirmed] (indefinite))

2010-12-04T07:47:13Z

Protected "ADD@" ([edit=autoconfirmed] (indefinite) [move=autoconfirmed] (indefinite))

Mr z at 16:27, 7 November 2007

2007-11-07T16:27:33Z

Mr z at 21:46, 7 October 2007

2007-10-07T21:46:35Z

Mr z at 21:39, 7 October 2007

2007-10-07T21:39:57Z

Mr z at 21:37, 7 October 2007

2007-10-07T21:37:56Z

Pingaso at 21:29, 12 January 2005

2005-01-12T21:29:07Z

New page

[[Category:CP1610]]
<table border>
<tr><td>Instruction Name</td><td>Add Indirect</td></tr>
<tr><td>Mnemonic</td><td>ADD@</td></tr>
<tr><td>CP1610 Clock Cycles</td><td>8, 10, or 11</td></tr>
<tr><td>Interruptible</td><td>Yes</td></tr>
<tr><td>Opcode Range</td><td>$02C0-$02C7</td></tr>
<tr><td>Input Flags</td><td>None</td></tr>
<tr><td>Output Flags</td><td>[[Sign Flag]], [[Zero Flag]], [[Overflow Flag]], [[Carry Flag]]</td></tr>
</table><br/>
The Add Indirect (ADD@) instruction adds the value at the address in the specified address register to the value in the specified destination register, stores the result in the destination register, and sets or clears the [[Sign Flag]], [[Zero Flag]], [[Overflow Flag]], and [[Carry Flag]] according to the result.<br/><br/>

If the [[Double Byte Data Flag]] is set, then this instruction will perform two indirect reads, using the lowest 8 bits of the first read as the lowest 8 bits of the resulting value and combining them with the lowest 8 bits of the second read as the highest 8 bits of the resulting value. Note that if the address register is R1-R3 (which do <strong>not</strong> auto-increment or auto-decrement), then the register value will not change between successive indirect reads, and thus the same value at the same address would be read for both indirect reads. If the [[Double Byte Data Flag]] is set, this instruction will always use exactly 10 clock cycles regardless of which register is used as the address register.<br/>

0000:0010:10aa:addd<br/>
where:
ddd indicates the register containing the value to move
such that:
ddd == 000 indicates register R0
ddd == 001 indicates register R1
ddd == 010 indicates register R2
ddd == 011 indicates register R3
ddd == 100 indicates register R4
ddd == 101 indicates register R5
ddd == 110 indicates register R6
ddd == 111 indicates register R7<br/>
aaa indicates the register containing the address
such that:
aaa == 000 indicates register R0
aaa == 001 indicates register R1
aaa == 010 indicates register R2
aaa == 011 indicates register R3
aaa == 100 indicates register R4
aaa == 101 indicates register R5
aaa == 110 indicates register R6
aaa == 111 indicates register R7<br/>

← Older revision		Revision as of 16:27, 7 November 2007
Line 11:		Line 11:
	The Add Indirect (ADD@) instruction adds the value at the address in the specified address register to the value in the specified destination register, stores the result in the destination register, and sets or clears the [[Sign Flag]], [[Zero Flag]], [[Overflow Flag]], and [[Carry Flag]] according to the result.<br/><br/>		The Add Indirect (ADD@) instruction adds the value at the address in the specified address register to the value in the specified destination register, stores the result in the destination register, and sets or clears the [[Sign Flag]], [[Zero Flag]], [[Overflow Flag]], and [[Carry Flag]] according to the result.<br/><br/>

−	If ~~the~~ [[~~Double Byte Data Flag~~]] ~~is set~~, ~~then~~ this instruction will perform two indirect reads, using the lowest 8 bits of the first read as the lowest 8 bits of the resulting value and combining them with the lowest 8 bits of the second read as the highest 8 bits of the resulting value. Note that if the address register is R1-R3 (which do <strong>not</strong> auto-~~increment or auto-decrement), then the register~~ value ~~will not change between successive indirect reads~~, and ~~thus the same value at the same address would be read for both indirect reads. If the [[Double Byte Data Flag]] is set, this instruction~~ will always use exactly 10 clock cycles regardless of which register is used as the address register.<br/>	+	If prefixed with [[SDBD]], this instruction will perform two indirect reads to build a 16-bit value for its first operand, and will always use exactly 10 clock cycles regardless of which register is used as the address register. See [[Double Byte Data]] for more details on how [[SDBD]] interacts with [[Indirect Mode]].<br/><br/>

@@ Line 14: / Line 14: @@
-:0010:10aa:addd<br/>
+:0010:11aa:addd<br/>
      where:
          ddd   indicates the register containing the value to move

← Older revision	Revision as of 07:47, 4 December 2010
(No difference)

@@ Line 34: / Line 34: @@
                    aaa == 100    indicates register R4
                    aaa == 101    indicates register R5
-                   aaa == 110    indicates register R6
+                   aaa == 110    indicates register R6, which operates in [[Stack Mode|stack mode]]
                    aaa == 111    indicates register R7, alias for [[Immediate Mode|immediate mode]] [[ADDI]]<br/>

@@ Line 28: / Line 28: @@
          aaa   indicates the register containing the address
                such that:
-                   aaa == 000    not allowed (aliases "direct mode" encoding)
+                   aaa == 000    indicates [[Direct Mode|direct mode]] [[ADD]] instruction
                    aaa == 001    indicates register R1
                    aaa == 010    indicates register R2
@@ Line 35: / Line 35: @@
                    aaa == 101    indicates register R5
                    aaa == 110    indicates register R6
-                   aaa == 111    indicates register R7 (equivalent to "immediate mode")<br/>
+                   aaa == 111    indicates register R7, alias for [[Immediate Mode|immediate mode]] [[ADDI]]<br/>