STIC Bus Request
During the active display time, the STIC needs to read background cards from BACKTAB while it generates the display. The STIC itself lacks storage for these cards. Instead, the System RAM provides a 20-entry video FIFO, which is sufficient to hold one row of background cards.
The STIC prepares the video FIFO for the next row of cards by asserting a bus request (BUSRQ) one scanline ahead of when it will need the cards on its SR2 output pin. The CPU acknowledges the STIC's request after the next interruptible instruction by asserting BUSAK (BUS request AcKnowledge). (Interrupts need not be enabled.) The CPU's BUSAK signal goes directly to the System RAM and to the GROM. The System RAM uses the pulse to advance its FIFO pointer, and to switch out of Bus Copy mode, if it was previously in that mode. The GROM uses this pulse to switch its memory decoding logic to a mode suitable for display generation.
When the STIC reaches the scanline where it needs the cards, it pulses its SR3 output once for each card. Pulsing SR3 while the CPU also asserts BUSAK causes the System RAM to copy one new card to the video FIFO from BACKTAB in addition to sending it to the STIC. As a result, the video FIFO fills with a new row of background cards. Once STIC moves a full row of cards to the video FIFO (and not coincidentally finishes the scanline), it deasserts BUSRQ. The CPU deasserts BUSAK and resumes processing.
On the next 15 scan lines, the STIC pulses SR3 when it needs a new card. The System RAM responds by replaying the same 20 background cards repeatedly from the video FIFO. The System RAM won't source new cards into the video FIFO until it sees another BUSAK from the CPU.
Thus, the STIC steals around 1 to 2 scanlines out of 16 from the CPU during active display to reload the video FIFO. If the CPU ignores the STIC's bus request, the System RAM will simply replay the same 20 cards again for the next 16 scanlines--in effect pushing the screen down an entire row and repeating the current one.