VBlank Period 2
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Latest revision as of 07:42, 4 December 2010
The STIC facilitates access to GRAM and GROM for only certain time periods as part of its vertical refresh duties. These time periods are anchored relative to the VBlank Interrupt that the STIC generates and the Bus Copy mode that the System RAM implements.
When the display's active, the GRAM and GROM are available for approximately 3796 cycles following the VBlank Interrupt. When the display is not active--that is, the program did not write to location $0020 (or its aliases at $4020, $8020 or $C020) during VBlank Period 1--the GRAM and GROM remain accessible until the program makes the display active.
This period is longer than VBlank Period 1.
No data is presently available for these systems. Given the lower refresh rate and higher clock rate of these systems, both VBlank Period 1 and VBlank Period 2 are probably longer than they are on the NTSC systems. New games should design for the tighter NTSC time windows.