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Revision as of 09:43, 4 December 2010
The STIC signals the VBlank Interrupt (short for "Vertical Blanking Interrupt") when it has finished drawing the active display, just as it begins to draw the solid border at the bottom of the screen. The STIC signals this interrupt by pulsing its SR1 output low. SR1 connects directly to the CP1610's INTRM input.
The VBlank Interrupt is important for two reasons:
- It provides a regular "pulse" upon which to base game timing and events.
- It signals the start of the VBlank Interval, which controls access to STIC registers, Graphics RAM and Graphics ROM.
On NTSC Intellivisions, the STIC asserts this signal once every 14394 cycles, and holds it asserted for exactly 3791 CP1610 clock cycles. On PAL/SECAM Intellivisions, the exact interrupt timing is unknown. In order to take the interrupt, the CP1610's Interrupt Enable Flag must be set, and the CPU must encounter at least one interruptible instruction while the STIC asserts SR1. Otherwise, the CPU will drop the interrupt.