Difference between revisions of "VBlank Interrupt"
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| − | The VBlank Interrupt (short for "Vertical Blanking Interrupt") is an interrupt signaled by the [[STIC]] when it has finished drawing the active display | + | The VBlank Interrupt (short for "Vertical Blanking Interrupt") is an interrupt signaled by the [[STIC]] by asserting low on SR1 (which is connected to the INTRM line on the [[CP1610]]) when it has finished drawing the active display, just as it begins to draw the solid border at the bottom of the screen. The VBlank Interrupt is important for two reasons: |
* It provides a regular "pulse" upon which to base game timing and events. | * It provides a regular "pulse" upon which to base game timing and events. | ||
* It signals the start of the [[VBlank Interval]], which controls access to STIC registers, [[Graphics RAM]] and [[Graphics ROM]]. | * It signals the start of the [[VBlank Interval]], which controls access to STIC registers, [[Graphics RAM]] and [[Graphics ROM]]. | ||
| − | On NTSC Intellivisions, this interrupt | + | On NTSC Intellivisions, the [[STIC]] stignals this interrupt once every 14394 cycles and it maintains this signal for exactly 3791 [[CP1610]] clock cycles. On PAL/SECAM Intellivisions, the exact interrupt timing is unknown. Note that if the [[Interrupt Enable Flag]] within the [[CP1610]] is clear for the entire duration of the signal from the [[STIC]], or if the [[CP1610]] simply never encounters an interruptible instruction during that time, the CP1610 will miss the interrupt altogether. This has been noted as a problem in particular for the game [[Dreadnaught Factor]]. |
Revision as of 18:52, 11 January 2005
The VBlank Interrupt (short for "Vertical Blanking Interrupt") is an interrupt signaled by the STIC by asserting low on SR1 (which is connected to the INTRM line on the CP1610) when it has finished drawing the active display, just as it begins to draw the solid border at the bottom of the screen. The VBlank Interrupt is important for two reasons:
- It provides a regular "pulse" upon which to base game timing and events.
- It signals the start of the VBlank Interval, which controls access to STIC registers, Graphics RAM and Graphics ROM.
On NTSC Intellivisions, the STIC stignals this interrupt once every 14394 cycles and it maintains this signal for exactly 3791 CP1610 clock cycles. On PAL/SECAM Intellivisions, the exact interrupt timing is unknown. Note that if the Interrupt Enable Flag within the CP1610 is clear for the entire duration of the signal from the STIC, or if the CP1610 simply never encounters an interruptible instruction during that time, the CP1610 will miss the interrupt altogether. This has been noted as a problem in particular for the game Dreadnaught Factor.
