SUB@

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Instruction NameSubtract Indirect
MnemonicSUB@
CP1610 Clock Cycles8, 10, or 11
InterruptibleYes
Opcode Range$0308-$032F
Input FlagsNone
Output FlagsSign Flag, Zero Flag, Overflow Flag, Carry Flag

The Subtract Indirect (SUB@) instruction subtracts the value at the address in the specified address register from the value in the specified destination register, stores the result in the destination register, and sets or clears the Sign Flag, Zero Flag, Overflow Flag, and Carry Flag according to the result.

If prefixed with SDBD, this instruction will perform two indirect reads to build a 16-bit value for its first operand, and will always use exactly 10 clock cycles regardless of which register is used as the address register. See Double Byte Data for more details on how SDBD interacts with Indirect Mode.


   0000:0011:00aa:addd
where: ddd indicates the register containing the value to move such that: ddd == 000 indicates register R0 ddd == 001 indicates register R1 ddd == 010 indicates register R2 ddd == 011 indicates register R3 ddd == 100 indicates register R4 ddd == 101 indicates register R5 ddd == 110 indicates register R6 ddd == 111 indicates register R7
aaa indicates the register containing the address such that: aaa == 000 indicates direct mode SUB instruction aaa == 001 indicates register R1 aaa == 010 indicates register R2 aaa == 011 indicates register R3 aaa == 100 indicates register R4 aaa == 101 indicates register R5 aaa == 110 indicates register R6, which operates in stack mode aaa == 111 indicates register R7, alias for immediate mode SUBI
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