SLL

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Instruction NameShift Logical Left
MnemonicSLL
CP1610 Clock Cycles6 or 8
InterruptibleNo
Opcode Range$0048-$004F
Input FlagsNone
Output FlagsSign Flag, Zero Flag

The Shift Logical Left (SLL) instruction shifts the bits in the specified register by either one (1) or two (2) bits to the left, stores the result back to the specified register, and sets or clears the Sign Flag and Zero Flag according to the new value in the register. The leftmost one or two bits are discarded and the rightmost one or two bits are set to zero(0). The number of clock cycles used depends on the number of shifts specified. One shift will use 6 clock cycles and two shifts will use 8 clock cycles.

Sll diagram.png


The opcode format is as follows.

   0000:0000:0100:1srr
where: s indicates the number of places to shift such that: s == 0 indicates to shift once s == 1 indicates to shift twice
rr indicates the target register such that: rr == 00 indicates register R0 rr == 01 indicates register R1 rr == 10 indicates register R2 rr == 11 indicates register R3
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