SLL

Instruction Name	Shift Logical Left
Mnemonic	SLL
CP1610 Clock Cycles	6 or 8
Interruptible	No
Opcode Range	$0048-$004F
Input Flags	None
Output Flags	Sign Flag, Zero Flag

The Shift Logical Left (SLL) instruction shifts the bits in the specified register by either one (1) or two (2) bits to the left, stores the result back to the specified register, and sets or clears the Sign Flag and Zero Flag according to the new value in the register. The leftmost one or two bits are discarded and the rightmost one or two bits are set to zero(0). The number of clock cycles used depends on the number of shifts specified. One shift will use 6 clock cycles and two shifts will use 8 clock cycles. The opcode format is as follows.

   0000:0000:0100:1srr

   where:
       s   indicates the number of places to shift
           such that:
               s == 0   indicates to shift once
               s == 1   indicates to shift twice

       rr  indicates the target register
           such that:
               rrr == 000   indicates register R0
               rrr == 001   indicates register R1
               rrr == 010   indicates register R2
               rrr == 011   indicates register R3