# SAR

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<tr><td>Output Flags</td><td>[[Sign Flag]], [[Zero Flag]]</td></tr> | <tr><td>Output Flags</td><td>[[Sign Flag]], [[Zero Flag]]</td></tr> | ||

</table><br/> | </table><br/> | ||

- | The Shift Arithmetic Right (SAR) instruction shifts the bits in the specified register either one (1) or two (2) bits to the right, stores the result back to the specified register, and sets or clears the [[Sign Flag]] and [[Zero Flag]] according to the new value in the register. The rightmost one or two bits are discarded. Unlike the [[SLR|Shift Logical Right]] instruction, however, the SAR instruction does not set the leftmost one or two bits to zero. Instead the value of bit 15 (the sign bit) stays the same value as the value of bit 15 before the shift occurred. For a double shift, bit 15 is also copied to bit 14. The number of clock cycles used depends on the number of shifts specified. One shift will use 6 clock cycles and two shifts will use 8 clock cycles. | + | The Shift Arithmetic Right (SAR) instruction shifts the bits in the specified register either one (1) or two (2) bits to the right, stores the result back to the specified register, and sets or clears the [[Sign Flag]] and [[Zero Flag]] according to the new value in the register. The rightmost one or two bits are discarded. Unlike the [[SLR|Shift Logical Right]] instruction, however, the SAR instruction does not set the leftmost one or two bits to zero. Instead the value of bit 15 (the sign bit) stays the same value as the value of bit 15 before the shift occurred. For a double shift, bit 15 is also copied to bit 14. The number of clock cycles used depends on the number of shifts specified. One shift will use 6 clock cycles and two shifts will use 8 clock cycles.<br/><br/> |

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+ | [[Image:Sar_diagram.png]] | ||

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+ | The opcode format is as follows.<br/><br/> | ||

0000:0000:0110:1srr<br/> | 0000:0000:0110:1srr<br/> |

## Revision as of 14:55, 8 October 2007

Instruction Name | Shift Arithmetic Right |

Mnemonic | SAR |

CP1610 Clock Cycles | 6 or 8 |

Interruptible | No |

Opcode Range | $0068-$006F |

Input Flags | None |

Output Flags | Sign Flag, Zero Flag |

The Shift Arithmetic Right (SAR) instruction shifts the bits in the specified register either one (1) or two (2) bits to the right, stores the result back to the specified register, and sets or clears the Sign Flag and Zero Flag according to the new value in the register. The rightmost one or two bits are discarded. Unlike the Shift Logical Right instruction, however, the SAR instruction does not set the leftmost one or two bits to zero. Instead the value of bit 15 (the sign bit) stays the same value as the value of bit 15 before the shift occurred. For a double shift, bit 15 is also copied to bit 14. The number of clock cycles used depends on the number of shifts specified. One shift will use 6 clock cycles and two shifts will use 8 clock cycles.

The opcode format is as follows.

0000:0000:0110:1srr

where: s indicates the number of places to shift such that: s == 0 indicates to shift once s == 1 indicates to shift twice

rr indicates the target register such that: rrr == 000 indicates register R0 rrr == 001 indicates register R1 rrr == 010 indicates register R2 rrr == 011 indicates register R3