Difference between revisions of "Double Byte Data"

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(Expound upon the wide ranging influence of SDBD)
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[[Category:CP1610]]
 
[[Category:CP1610]]
The Double Byte Data Flag (D) is set when the [[SDBD]] instruction is executed.  This flag causes the next instruction, if it is an [[Indirect]] mode instruction, to load the 16-bit operand from the lowest 8 bits of two consecutive memory locations, rather than all 16-bits of a single memory location. Note that the D flag only remains set for the next executed opcode, regardless of whether of not the next opcode is actually affected by the status of the Double Byte Data Flag. After execution of the next opcode, the Double Data Flag is automatically cleared.<br/>
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The [[SDBD|Set Double Byte Data]] instruction sets the Double Byte Data Flag (D).  This flag causes the next instruction, if it is an [[Indirect]] mode [[Immediate]] mode instruction, to issue two memory reads instead of one, and construct a 16-bit operand from the lowest 8 bits from the values it read.  The first read fills the lower 8 bits of the result, and the second read fills the upper 8 bits.  SDBD also [[Undocumented SDBD Behavior|modifies the behavior of Direct mode accesses]]<br/>
 
<br/>
 
<br/>
The behavior of the following opcodes is affected by the status of the Double Byte Data Flag.<br/>
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For [[Immediate]] mode accesses, the CPU reads the two locations immediately following the instruction.  This allows ROMs narrower than 16 bits to hold immediate constants up to 16 bits long.<br/>
 
<br/>
 
<br/>
[[MVI@]]<br/>
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For [[Indirect]] mode accesses, if the indirect register is auto-incrementing (R4 or R5), the two values read come from consecutive addresses.  If the indirect register is not auto-incrementing (R1, R2 or R3), the instruction reads the same location twice.  The [[CP1610]] does not specifically support SDBD with [[Indirect]] accesses through the stack pointer.  Programs also must be careful not to use the same register both as a numeric operand and an indirect register when accessing Double Byte Data.  In both of these cases, [[Undocumented SDBD Behavior|strange behavior results]].<br/>
[[ADD@]]<br/>
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<br/>
[[SUB@]]<br/>
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Note that the D flag only remains set for the next executed opcode, regardless of whether of not the next opcode is actually affected by the status of the Double Byte Data Flag. After execution of the next opcode, the CPU clears the Double Byte Data Flag automatically.<br/>
[[CMP@]]<br/>
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<br/>
[[AND@]]<br/>
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The Double Byte Data Flag affects the behavior of the following instructions:<br/>
[[XOR@]]<br/>
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<table cellpadding=5>
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<tr><td>[[MVI@]]</td><td>[[MVII]]</td><td>[[MVI]]</td></tr>
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<tr><td>[[ADD@]]</td><td>[[ADDI]]</td><td>[[ADD]]</td></tr>
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<tr><td>[[SUB@]]</td><td>[[SUBI]]</td><td>[[SUB]]</td></tr>
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<tr><td>[[CMP@]]</td><td>[[CMPI]]</td><td>[[CMP]]</td></tr>
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<tr><td>[[AND@]]</td><td>[[ANDI]]</td><td>[[AND]]</td></tr>
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<tr><td>[[XOR@]]</td><td>[[XORI]]</td><td>[[XOR]]</td></tr></table>

Revision as of 22:13, 11 January 2005

The Set Double Byte Data instruction sets the Double Byte Data Flag (D). This flag causes the next instruction, if it is an Indirect mode Immediate mode instruction, to issue two memory reads instead of one, and construct a 16-bit operand from the lowest 8 bits from the values it read. The first read fills the lower 8 bits of the result, and the second read fills the upper 8 bits. SDBD also modifies the behavior of Direct mode accesses

For Immediate mode accesses, the CPU reads the two locations immediately following the instruction. This allows ROMs narrower than 16 bits to hold immediate constants up to 16 bits long.

For Indirect mode accesses, if the indirect register is auto-incrementing (R4 or R5), the two values read come from consecutive addresses. If the indirect register is not auto-incrementing (R1, R2 or R3), the instruction reads the same location twice. The CP1610 does not specifically support SDBD with Indirect accesses through the stack pointer. Programs also must be careful not to use the same register both as a numeric operand and an indirect register when accessing Double Byte Data. In both of these cases, strange behavior results.

Note that the D flag only remains set for the next executed opcode, regardless of whether of not the next opcode is actually affected by the status of the Double Byte Data Flag. After execution of the next opcode, the CPU clears the Double Byte Data Flag automatically.

The Double Byte Data Flag affects the behavior of the following instructions:

MVI@MVIIMVI
ADD@ADDIADD
SUB@SUBISUB
CMP@CMPICMP
AND@ANDIAND
XOR@XORIXOR