CP1610

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Revision as of 16:40, 11 January 2005 by 209.108.192.30 (talk) (Flags)
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The CPU used in the Intellivision Master Component is a General Instruments CP1610. The CP1610 is a general purpose microprocessor capable of supporting 16-bit addresses and 10-bit instructions.

Overview

Clock Speed894,886.25 Hz
Address Width16-bit
Instruction Width10-bit
Reset Address$1000
Interrupt Address$1004
FlagsS, Z, O, C, I, D, inter
RegistersR0, R1, R2, R3, R4, R5, R6, R7
Signal PinsINTRM, BUSRQ, BUSAK
External PinsEXT


General Behavior

The R7 register behaves as program counter for the CP1610. On the Intellivision, the CP1610 initializes R7 to the value $1000. The CP1610 then reads, decodes, and executes the opcode at the location reference by R7 and the increments R7 to the next instruction. It repeats this behavior indefinitely, or until a HLT instruction is read.

Although most opcodes are only one memory location in length (one 10-bit value or "decle"), a few opcodes stretch to two or three memory locations, causing R7 to increment by more than a single value in order to find the next instruction to execute. The processor receives hardware interrupts from the STIC which occur once per screen refresh. The STIC may also request the CP1610 temporarily halt processing to allow the STIC to perform direct memory accesses.

Flags

SSign FlagIf set, indicates that the previous operation resulted in negative value, which is determined by a one (1) in bit 15 of the result.
CCarry FlagIf set, indicates that the previous operation resulted in unsigned integer overflow.
ZZero FlagIf set, indicates that the previous operation resulted in zero.
OOverflow FlagIf set, indicates that the previous operation gave a signed result that is inconsistent with the signs of the source operands. (Signed overflow.)
IInterrupt Enable FlagIf set, allows the INTRM line to trigger an interrupt, causing the CPU to jump to the interrupt subroutine located in the Executive ROM at $1004.
DDouble Data FlagIf set, it causes the next opcode, if it is capable of operating on a 16-bit operand, to load the 16-bit operand from the lowest 8 bits of two consecutive memory locations, rather than all 16-bits of a single memory location.

Special notes:

  • The S, C, Z, and O flags are directly visible to the programmer via the GSWD instruction. The I and D flags are internal to the CPU, and not visible directly visible to the programmer.
  • The C and O flags serve a secondary purpose for the shift and rotate instructions. The SLLC, SARC, RLC and RRC use the C and O flags to store bits that get "shifted away." Also, the RLC and RRC instructions "shift in" the bits stored in C and O.
  • The S flag takes on a special role also with the shift instructions. The SWAP, SLR, SAR, SARC and RRC instructions set the S flag based on bit 7 of the result, rather than bit 15.

Signal Pins

SignalNameDirectionPurposeUse on Intellivision
INTRMINTerrupt Request, Masked.Input A high-to-low transition on this pin causes the CPU to take an interrupt if interrupts are enabled. If the signal transitions back to the "high" state prior to taking the interrupt, the CPU will ignore the interrupt.Connects to the SR1 output pin on the STIC. The STIC signals VBlank Interrupt to the CP1610 on this pin, and the CP1610 jumps to the interrupt vector at $1004 after the next interruptible instruction.
INTRINTerrupt Request.Input A high-to-low transition on this pin causes the CPU to take an interrupt, regardles of whether interrupts are enabled.The Intellivision leaves this signal tied to +5v (deasserted).
BUSRQBUS ReQuest.Input A high-to-low transition on this pin requests that the CPU halt so that something else may access the bus. Connects to the SR2 output pin on the STIC. The STIC signals the CP1610 on this pin at points during active display when it needs to access System RAM. The CP1610 halts after the next interruptible instruction, regardless of whether interrupts are enabled.
BUSAKBUS AcKnowledge.Output Asserted (active-low output) when the CPU has yielded the bus. Connects to the SST input pins on the System RAM and the GROM. The CP1610 acknowledges the STIC's bus request by signaling to the System RAM and GROM that it halted by request of the STIC.
MSYNCMaster SYNC.Input Asserting this signal (active low) resets the CPU and synchronizes it to its clocks. Connects to the MSYNC output of the STIC. The STIC generates this signal shortly after powerup after the clock stabilizes, or whenever someone releases the reset button or asserts RESET on the cartridge port.
EBCA0 - EBCA3External Branch Condition Address.Output The four outputs EBCA0 through EBCA3, along with the single input ECBI provide a mechanism for external hardware to generate branch control inputs to the CPU. The BEXT instruction includes a 4-bit field that the CP1610 asserts on EBCA0 - EBCA3. External hardware then asserts a 0 or 1 on EBCI to indicate whether to take the branch. This allows up to 16 different branch conditions to be asserted to the CPU. These pins are not connected in the Intellivision, so the BEXT instruction is typically never used.
EBCIExternal Branch Condition Input.Input
TCITerminate Current Interrupt.Output TCI is both an instruction as well as a pin on the device. The TCI instruction pulses the TCI pin on the CP1610. The Intellivision leaves this signal unconnected, and so the TCI instruction is effectively a NOP.
PCITProgram Counter Inhibit/Trap.Bidirectional. External hardware can prevent the CPU from incrementing the program counter by asserting this signal. The SIN instruction generates a pulse on this line. The Intellivision leaves this signal tied to +5v (deasserted) through a resistor.
STPSTSToP-STart.InputStops or starts the execution of the CPU whenever it sees a high-to-low transition.The Intellivision leaves this signal tied to +5v.
HALTHALTed.OutputIndicates the CPU halted.The Intellvision leaves this signal unconnected.
BDRDYBus Data ReaDY.InputWhen deasserted, it causes the CPU to wait for data to become available on the bus, effectively inserting wait states.The Intellivision leaves this signal unconnected, and thus has no notion of wait states.

Interruptibility

Each CP1610 opcode is considered either "interruptible" or "not interruptible". The interruptibility of an opcode determines whether or not the CP1610 checks the status of INTRM and BUSRQ after executing that instruction, and prior to executing the next. The CP1610 will only check for an interrupt request signaled via INTRM only if the I flag is set and only after the next interruptible instruction. Note that the signal from the STIC via INTRM is only alive for the duration of vertical blank, exactly 3,791 CP1610 clock cycles. If the I flag is clear for that entire duration, or if the CP1610 never encounters an interruptible instruction during that time, the CP1610 will miss the interrupt altogether. I have personally noticed this as a problem in particular for the game Dreadnaught Factor.

Similarly, the CP1610 only receives a signal from the STIC via BUSRQ for a total of exactly 114 CP1610 clock cycles. Although unaffected by the status of the I flag, if the CP1610 nonetheless encounters a stream of uninterruptible instructions, it will miss the chance to halt altogether and will fail to signal back to the STIC on BUSAK. The STIC, in turn, will fail to perform the necessary direct memory accesses to fetch the next row of cards to display. The exact behavior of the Intellivision hardware is unknown if this occurs, but it is believed to likely render a duplicate of the previous row of cards.

Registers

TBD

Instruction Set

Below is a detailed breakdown of all the opcodes available as a part of the CP1610 instruction set. This information is somewhat incomplete at the moment, but will be filled out a bit more in the near future.

RangeInstructionMnemonicOpcodeFlags
$0000HaLTHLT0000:0000:0000:0000 
$0001Set DouBle DataSDBD0000:0000:0000:0001
$0002Enable Interrupt SystemEIS0000:0000:0000:0010
$0003Disable Interrupt SystemDIS0000:0000:0000:0011
$0004JumpJ/JD/JE/J@
JSR/JSRD/JSRE/JSR@
0000:0000:0000:0100
$0005Terminate Current InterruptTCI0000:0000:0000:0101
$0006CLeaR CarryCLRC0000:0000:0000:0110
$0007SET CarrySETC0000:0000:0000:0111
$0008-$000FINCrement RegisterINCR0000:0000:0000:1rrr
rrr = target register
$0010-$0017DECrement RegisterDECR0000:0000:0001:0rrr
rrr = target register
$0018-$001FCOMplement RegisterCOMR0000:0000:0001:1rrr
rrr = target register
$0020-$0027NEGate RegisterNEGR0000:0000:0010:0rrr
rrr = target register
$0028-$002FADd Carry to RegisterADCR0000:0000:0010:1rrr
rrr = target register
$0030-$0033Get the Status WorDGSWD0000:0000:0011:00rr
rr = target register
$0034-$0035No OPerationNOP0000:0000:0011:010x
x = ignored
$0036-$0037Software INterruptSIN0000:0000:0011:011x
x = ignored
$0038-$003FReturn Status WorDRSWD0000:0000:0011:1rrr
rrr = target register
$0040-$0047SWAP bytesSWAP0000:0000:0100:0srr
s: 0 = swap once, 1 = swap twice
rr = target register
$0048-$004FShift Logical LeftSLL0000:0000:0100:1srr
s = shift count
rr = target register
$0050-$0057Rotate Left through CarryRLC0000:0000:0101:0srr
s = rotate count
rr = target register
$0058-$005FShift Logical Left through CarrySLLC0000:0000:0101:1srr
s = shift count
rr = target register
$0060-$0067Shift Logical RightSLR0000:0000:0110:0srr
s = shift count
rr = target register
$0068-$006FShift Arithmetic RightSAR0000:0000:0110:1srr
s = shift count
rr = target register
$0070-$0077Rotate Right through CarryRRC0000:0000:0111:0srr
s = rotate count
rr = target register
$0078-$007FShift Arithmetic Rightthrough CarrySARC0000:0000:0111:1srr
s = shift count
rr = target register
$0080-$00BFMOVe RegisterMOVR0000:0000:10ss:sddd
sss = source register
ddd = destination register
$00C0-$00FFADD RegistersADDR0000:0000:11ss:sddd
sss = source register
ddd = destination register
$0100-$013FSUBtract RegistersSUBR0000:0001:00ss:sddd
sss = source register
ddd = destination register
$0140-$017FCoMPare RegistersCMPR0000:0001:01ss:sddd
sss = source register
ddd = destination register
$0180-$01BFAND RegistersANDR0000:0001:10ss:sddd
sss = source register
ddd = destination register
$01C0-$01FFXOR RegistersXORR0000:0001:11ss:sddd
sss = source register
ddd = destination register
$0200-$023FBranchB/BC/BOV/BPL
BEQ/BLT/BLE/BUSC
NOPP/BNC/BNOV/BMI
BNEQ/BGE/BGT/BESC
BEXT
0000:0010:00de:nccc
d = direction
e = external
n = negation
ccc = condition
$0240-$0247MoVe OutMVO0000:0010:0100:0rrr
rrr = register to move
$0248-$027FMoVe Out IndirectMVO@0000:0010:01ss:srrr
sss = register with address (not zero)
rrr = register to move
$0280-$0287MoVe InMVI0000:0010:1000:0rrr
rrr = register to move
$0288-$02BFMoVe In IndirectMVI@0000:0010:01ss:srrr
sss = register with address (not zero)
rrr = register to move
$02C0-$02C7ADDADD0000:0010:0100:0rrr
rrr = register to store result
$02C8-$02FFADD IndirectADD@0000:0010:01ss:srrr
sss = register with address (not zero)
rrr = register to move
$0300-$0307SUBtractSUB0000:0010:0100:0rrr
rrr = register to store result
$0308-$033FSUBtract IndirectSUB@0000:0010:01ss:srrr
sss = register with address (not zero)
rrr = register to move
$0340-$0347CoMPareCMP0000:0010:0100:0rrr
rrr = register to store result
$0348-$037FCoMPare IndirectCMP@0000:0010:01ss:srrr
sss = register with address (not zero)
rrr = register to move
$0380-$0387ANDAND0000:0010:0100:0rrr
rrr = register to store result
$0388-$03BFAND IndirectAND@0000:0010:01ss:srrr
sss = register with address (not zero)
rrr = register to move
$03C0-$03C7XORXOR0000:0010:0100:0rrr
rrr = register to store result
$03C8-$03FFXOR IndirectXOR@0000:0010:01ss:srrr
sss = register with address (not zero)
rrr = register to store result