CMPR
| Instruction Name | Compare Registers |
| Mnemonic | CMPR |
| CP1610 Clock Cycles | 6 |
| Interruptible | Yes |
| Opcode Range | $0140-$017F |
| Input Flags | None |
| Output Flags | Sign Flag, Zero Flag, Overflow Flag, Carry Flag |
The Compare Registers (CMPR) instruction is functionally identical to the Subtract Registers instruction except that it does not store the resulting value in the destination register. The Compare Registers instruction subtracts the value in the specified source register from the value in the specified destination register and sets or clears the Sign Flag, Zero Flag, Overflow Flag, and Carry Flag according to the result, but the final result is not stored in the destination register, leaving both registers unchanged.
0000:0001:01ss:sddd
where: sss indicates the source register such that: sss == 000 indicates register R0 sss == 001 indicates register R1 sss == 010 indicates register R2 sss == 011 indicates register R3 sss == 100 indicates register R4 sss == 101 indicates register R5 sss == 110 indicates register R6 sss == 111 indicates register R7
ddd indicates the destination register such that: ddd == 000 indicates register R0 ddd == 001 indicates register R1 ddd == 010 indicates register R2 ddd == 011 indicates register R3 ddd == 100 indicates register R4 ddd == 101 indicates register R5 ddd == 110 indicates register R6 ddd == 111 indicates register R7
