Bus Phases

The CP1610 defines several "bus phases." These are the transaction types indicated on the BC1, BC2 and BDIR pins of the CPU. Peripherals decode the bus phase to determine the following, among other things:

• Whether there's a valid value on the bus
• Whether the value's an address or data
• Whether the current access is a read or a write

The following table describes the CP1610's various bus phases.

General Instruments Bus Protocol

BDIR	BC2	BC1	Mnemonic	Name	Description
0	0	0	NACT	No ACTion	During this stage, no device is active on the bus. DB0 through DB15 are allowed to float, with their previous driven value fading away during this phase.
0	0	1	ADAR	Address Data to Address Register	This bus phase is issued by the CPU during a Direct Addressing Mode instruction. Prior to this phase, an address will have been latched in a device by a prior BAR or ADAR bus phase. Then, during this phase, the currently selected device responds with its data on the bus, and at the end of this phase, all devices should latch this address as the address for the next memory access (DTB, DW, or DWS phases). The CPU asserts nothing during this phase -- rather, it expects the currently addressed device to inform the rest of the machine of the address for the next access.
0	1	0	IAB	Interrupt Address to Bus	This bus phase is entered during interrupt processing, after the current program counter has been written to the stack. It's also entered into on the first cycle after coming out of RESET. During this phase, an external device should assert the address of the Interrupt or RESET vector as appropriate. The CPU then moves this address into the program counter and resumes execution.
0	1	1	DTB	Data To Bus	This phase is entered during a read cycle. During this phase, the currently addressed device should assert its data on the bus. The CPU then reads this data.
1	0	0	BAR	Bus to Address Register	During this phase, the CPU asserts the address for the current memory access. All devices on the bus are expected to latch this address and perform address decoding at this time.
1	0	1	DW	Data Write	The DW and DWS bus phases initiate a write cycle. They always occur together on adjacent cycles, with data remaining stable on the bus across the transition from DW to DWS. During these phases, the data being written is available for external memories to latch. The CP-1600 allows two full CPU cycles for external RAM to latch the data.
1	1	0	DWS	Data Write Strobe
1	1	1	INTAK	INTerrupt AcKnowledge	The CPU enters this bus phase on the first cycle of interrupt processing. During the phase, the CPU places the current stack pointer value on the bus as it prepares to "push" the current program counter on the stack. Devices are expected to treat INTAK similarly to a BAR bus phase. Indeed, on the Intellivision Master Component, only the 16-bit System RAM sees the INTAK bus phase. It uses this bus phase to trigger a special bus-copy mode as well as for latching the current address. For all other devices in the system, INTAK is remapped to BAR by some discrete logic, and so is processed as a normal addressing cycle elsewhere.