Bus Phases

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The CP1610 defines several "bus phases." These are the transaction types indicated on the BC1, BC2 and BDIR pins of the CPU. Peripherals decode the bus phase to determine the following, among other things:


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Bus Phases

The Intellivision is built around a bidirectional, multiplexed address/data bus. This means the same lines are used alternately for address and data, and that each transaction is divided into multiple phases. Hardware external to the CPU must latch the address for a transaction while it's available. A future bus phase will read or write data at that address. The BC1, BC2 and BDIR control lines indicate what bus phase is currently active.

Most devices associated with the Intellivision latch addresses internally. The only exceptions appear to be the Graphics RAM and Scratchpad RAM, which rely on the Graphics ROM and Executive ROM to latch addresses for them, respectively. In the descriptions that follow, references to "Address Register" refer to this latch.

The following table describes the CP1610's various bus phases.

General Instruments Bus Protocol
BDIR BC2 BC1 Mnemonic Name Description
000NACT No ACTion During this stage, no device is active on the bus. DB0 through DB15 float to all ones (1), with their previous driven value fading away during this phase.
001ADAR Address Data to Address Register The CPU issues ADAR during a Direct Addressing Mode instruction. Prior to ADAR, a previous BAR or ADAR latches an address in all the device's address registers. During this phase, the currently selected device responds with its data on the bus. At the end of this phase, all devices should latch that data as the next "current address." A subsequent DTB, DW, DWS or ADAR will access the newly selected location. The CPU asserts nothing during this phase. Rather, it expects the currently addressed device to inform the rest of the machine of the address for the next access.
010IAB Interrupt Address to Bus The CPU issues this phase in response to an interrupt, after it wrties the current program counter to the stack. The CPU also issues IAB on the first cycle after coming out of RESET. During this phase, an external device asserts the address of the Interrupt or RESET vector as appropriate. The CPU moves this address into the program counter and resumes execution.
011DTB Data To Bus The CPU issues this phase during a read cycle. In response to DTB, the currently addressed device asserts its data on the bus. The CPU reads this data.
100BAR Bus to Address Register During this phase, the CPU asserts the address for the current memory access. All devices on the bus latch and decode the address at this time.
101DW Data Write The DW and DWS bus phases together form the write cycle. The CPU always issues DW and DWS consecutively, while it holds the data it's writing stable across both cycles. Thus, the CP-1600 allows two full CPU cycles for external RAM to latch the data. The addressed device can sample the data on either cycle, or use both if it needs it.
110DWS Data Write Strobe
111INTAK INTerrupt AcKnowledge The CPU issues INTAK in response to an interrupt. During the phase, the CPU places the current stack pointer value on the bus as it prepares to "push" the current program counter on the stack. Devices are expected to treat INTAK similarly to a BAR bus phase. Indeed, the Intellivision Master Component only lets the 16-bit System RAM see the INTAK bus phase. The Intellivision remaps INTAK to BAR with discrete logic for all other devices. The System RAM uses INTAK to trigger a special Bus Copy mode in addition to latching the current address.


Transaction Types

The CP-1600's bus transactions typically last between 4 and 7 CPU cycles. Half of these cycles are NACT cycles, inserted as spacing cycles between the activity cycles. As a general rule, there is a NACT cycle inserted after every cycle except in two specific cases. The first is between DW and DWS, which always occur back-to-back. The second is during an indirect access after an SDBD instruction, where the CPU omits NACT states after both DTBs.

The tables below illustrate the various bus transations, complete with a cycle-by-cycle description of the transaction.


Instruction Fetch or Indirect/Immediate-Mode Data Read

Cycle Phase Description
1 BAR CPU asserts address of the Instruction or Data to read. Devices should latch the address at this time and perform address decoding.
2 NACT The CPU deasserts the bus, and no other bus activity occurs during this cycle.
3 DTB The addressed device asserts its data on the bus. The CPU then reads this data.
4 NACT The device deasserts the bus, and no other bus activity occurs during this cycle.


Indirect/Immediate Addressing Mode Read with SDBD

Cycle Phase Description
1 BAR CPU asserts address of the lower byte of Data to read. Devices should latch the address at this time and perform address decoding.
2 NACT The CPU deasserts the bus, and no other bus activity occurs during this cycle.
3 DTB The addressed device asserts its data on the bus. The CPU then reads this data.
4 BAR The device deasserts the bus during the first quarter of this cycle, and the CPU asserts a new address for the upper byte of Data during the latter half of this cycle. Notice that there is no NACT spacing cycle before this BAR!
5 NACT The CPU deasserts the bus, and no other bus activity occurs during this cycle.
6 DTB The addressed device asserts its data on the bus. The CPU then reads this data. As with cycle 3, there is no NACT spacing cycle after this cycle!


Indirect/Immediate-Mode Data Write

Cycle Phase Description
1 BAR CPU asserts address of the Data to write. Devices should latch the address at this time and perform address decoding.
2 NACT The CPU deasserts the bus, and no other bus activity occurs during this cycle.
3 DW The CPU asserts the data to be written. The addressed device can latch the data at this time, although it is not necessary yet, as the data is stable through the next phase.
4 DWS The CPU continues to assert the data to be written. The addressed device can latch the data at this time if it hasn't already.
5 NACT The CPU deasserts the bus, and no other bus activity occurs during this cycle.


Direct Addressing Mode Read

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Cycle Phase Description
1 BAR CPU asserts address of the Instruction or Data to read. Devices should latch the address at this time and perform address decoding.
2 NACT The CPU deasserts the bus, and no other bus activity occurs during this cycle.
3 ADAR The addressed device asserts the data that is at the location addressed during BAR. This data is then latched as an address by all devices for a subsequent DTB bus phase. The CPU remains off the bus during this cycle.
4 NACT The device deasserts the bus, and no other bus activity occurs during this cycle.
5 DTB The newly-addressed device (the one whose address was given during ADAR) asserts its data on the bus. The CPU then reads this data.
6 NACT The device deasserts the bus, and no other bus activity occurs during this cycle.


Direct Addressing Mode Write

Cycle Phase Description
1 BAR CPU asserts address of the Data to write. Devices should latch the address at this time and perform address decoding.
2 NACT The CPU deasserts the bus, and no other bus activity occurs during this cycle.
3 ADAR The addressed device asserts the data that is at the location addressed during BAR. This data is then latched as an address by all devices for subsequent DW and DWS bus phase. The CPU remains off the bus during this cycle.
4 NACT The device deasserts the bus, and no other bus activity occurs during this cycle.
5 DW The CPU asserts the data to be written. The newly-addressed device (the one whose address was given during ADAR) can latch the data at this time, although it is not necessary yet, as the data is stable through the next phase.
6 DWS The CPU continues to assert the data to be written. The addressed device can latch the data at this time if it hasn't already.
7 NACT The CPU deasserts the bus, and no other bus activity occurs during this cycle.


Interrupt Processing

(Note: We are unsure about the NACTs at the end.)

Interrupt Processing
Cycle Phase Description
1 INTAK The CPU asserts the current Stack Pointer address (the value in R6), and increments the stack pointer internally. Devices are expected to latch this address and decode it internally. Also, devices are expected to take any special interrupt-acknowledgement steps at this time. (On the Intellivision, this bus phase is remapped to BAR for most devices. The only device that sees INTAK is the 16-bit System RAM.)
2 NACT The CPU deasserts the bus, and no other bus activity occurs during this cycle.
3 DW The CPU outputs the current program counter address. The device addressed during INTAK should latch the data either now or during the next cycle (DWS).
4 DWS The CPU continues to assert the current program counter address. If the addressed device hasn't done so already, it should latch the data now.
5 NACT The CPU deasserts the bus, and no other bus activity occurs during this cycle.
6 IAB An external device asserts the new program counter address (the address of the interrupt service routine) on the bus. The CPU latches this address and transfers it to the program counter. On the Intellivision, one of the EXEC's ROM chips asserts the reset and interrupt addresses for the CPU.
7 NACT The device deasserts the bus, and no other bus activity occurs during this cycle.
8 NACT The CPU inserts three more NACT cycles before resuming processing.
9 NACT
10 NACT
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