Bus Copy

The System RAM serves as a bridge between the CPU's main busses and the STIC's private graphics bus. During the VBlank Interval, the System RAM enters Bus Copy mode to allow the CPU access to the STIC's registers, as well as the GRAM and GROM. The System RAM exits Bus Copy mode when it sees a BUSAK signal from the CP-1610 CPU. This usually occurs just before the STIC starts active display at the end of VBlank Period 2.

The CPU's main address/data bus is 16 bits wide, whereas the STIC's graphics bus is only 14 bits wide. This leads to several interesting phenomena:

• The STIC ignores upper 2 bits of each word in BACKTAB. Programs can (and do) use them as flag bits.
• The STIC does not completely decode CPU addresses, primarily because it can only see 14 of the 16 address bits.
• The System RAM does see the full 16 bit address, leading to some oddities:
  • If the address was in the range $4000 - $FFFF, the System RAM refuses to forward the STIC's responses to reads back to the CPU. Thus, one cannot read the contents of GRAM, GROM or STIC registers at any of their aliases.
  • System RAM always copies through writes, however, leading to several dubiously usable write-only aliases in the Memory Map.
  • The STIC decodes bus phases separately from the System RAM. Thus, programs can switch between Foreground/Background and Color Stack modes by accessing any one of location $21's aliases, since it's simply the access itself and not the data transfered that sets the mode.