Difference between revisions of "Bus Copy"
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| − | The [[System RAM]] serves as a bridge between the CPU's main busses and the STIC's private graphics bus. During the [[VBlank Interval]], the System RAM enters Bus Copy mode to allow the CPU access to the [[STIC]]'s registers, as well as the [[GRAM]] and [[GROM]]. The System RAM exits Bus Copy mode when it sees a [[BUSAK]] signal from the CP-1610 CPU. This usually occurs just before the STIC starts active display at the end of [[VBlank Period 2]]. | + | The [[System RAM]] serves as a bridge between the CPU's main busses and the STIC's private graphics bus. During the [[VBlank Interval]], the System RAM enters Bus Copy mode to allow the CPU access to the [[STIC]]'s registers, as well as the [[Graphics RAM|GRAM]] and [[Graphics ROM|GROM]]. The System RAM exits Bus Copy mode when it sees a [[BUSAK]] signal from the CP-1610 CPU. This usually occurs just before the STIC starts active display at the end of [[VBlank Period 2]]. |
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| + | The CPU's main address/data bus is 16 bits wide, whereas the STIC's graphics bus is only 14 bits wide. This leads to several interesting phenomena: | ||
| + | * The STIC ignores upper 2 bits of each word in [[BACKTAB]]. Programs can (and do) use them as flag bits. | ||
| + | * The STIC [[Incomplete_Address_Decoding|does not completely decode CPU addresses]], primarily because it can only see 14 of the 16 address bits. | ||
| + | * The System RAM <I>does</I> see the full 16 bit address, and so refuses respond to reads outside the first 16K of the address map. But, it always copies through writes, leading to several write-only aliases in the [[Memory Map]]. | ||
Revision as of 07:42, 11 January 2005
The System RAM serves as a bridge between the CPU's main busses and the STIC's private graphics bus. During the VBlank Interval, the System RAM enters Bus Copy mode to allow the CPU access to the STIC's registers, as well as the GRAM and GROM. The System RAM exits Bus Copy mode when it sees a BUSAK signal from the CP-1610 CPU. This usually occurs just before the STIC starts active display at the end of VBlank Period 2.
The CPU's main address/data bus is 16 bits wide, whereas the STIC's graphics bus is only 14 bits wide. This leads to several interesting phenomena:
- The STIC ignores upper 2 bits of each word in BACKTAB. Programs can (and do) use them as flag bits.
- The STIC does not completely decode CPU addresses, primarily because it can only see 14 of the 16 address bits.
- The System RAM does see the full 16 bit address, and so refuses respond to reads outside the first 16K of the address map. But, it always copies through writes, leading to several write-only aliases in the Memory Map.
