Bus Copy

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Latest revision as of 08:08, 4 December 2010

The System RAM serves as a bridge between the CPU's main busses and the STIC's private graphics bus. At the start of the VBlank Interval (or more correctly, when the System RAM sees the CPU issue "INTAK" in response to the STIC's VBlank Interrupt), the System RAM enters Bus Copy mode. This allows the CPU access to the STIC's registers, as well as the GRAM and GROM. The System RAM exits Bus Copy mode when it sees a BUSAK signal from the CP-1610 CPU. This usually occurs just before the STIC starts active display at the end of VBlank Period 2.

Bus Copy mode is a very simple mode in which the System RAM simply copies all values on the CPU's address and data bus to the STIC's graphics bus. The System RAM reverses the direction of the copy only when the address currently being accessed is in the range $0000-$007F or $3000-$3FFF, and the current Bus Phase is DTB (Data To Bus). (It may also reverse the direction during the ADAR bus phase, but it appears System RAM treats ADAR the same as BAR.) The System RAM does not copy the bus phase through to the STIC, GRAM and GROM. Rather, the STIC looks directly at the bus phase, and decodes it on behalf of the GRAM and GROM.

The CPU's main address/data bus is 16 bits wide, whereas the STIC's graphics bus is only 14 bits wide. The System RAM decodes all 16 bits, whereas the STIC cannot. This leads to several interesting phenomena:

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