ADD@

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The Add Indirect (ADD@) instruction adds the value at the address in the specified address register to the value in the specified destination register, stores the result in the destination register, and sets or clears the [[Sign Flag]], [[Zero Flag]], [[Overflow Flag]], and [[Carry Flag]] according to the result.<br/><br/>
The Add Indirect (ADD@) instruction adds the value at the address in the specified address register to the value in the specified destination register, stores the result in the destination register, and sets or clears the [[Sign Flag]], [[Zero Flag]], [[Overflow Flag]], and [[Carry Flag]] according to the result.<br/><br/>
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If the [[Double Byte Data Flag]] is set, then this instruction will perform two indirect reads, using the lowest 8 bits of the first read as the lowest 8 bits of the resulting value and combining them with the lowest 8 bits of the second read as the highest 8 bits of the resulting value. Note that if the address register is R1-R3 (which do <strong>not</strong> auto-increment or auto-decrement), then the register value will not change between successive indirect reads, and thus the same value at the same address would be read for both indirect reads.  If the [[Double Byte Data Flag]] is set, this instruction will always use exactly 10 clock cycles regardless of which register is used as the address register.<br/>
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If prefixed with [[SDBD]], this instruction will perform two indirect reads to build a 16-bit value for its first operand, and will always use exactly 10 clock cycles regardless of which register is used as the address register. See [[Double Byte Data]] for more details on how [[SDBD]] interacts with [[Indirect Mode]].<br/><br/>

Revision as of 16:27, 7 November 2007

Instruction NameAdd Indirect
MnemonicADD@
CP1610 Clock Cycles8, 10, or 11
InterruptibleYes
Opcode Range$02C0-$02C7
Input FlagsNone
Output FlagsSign Flag, Zero Flag, Overflow Flag, Carry Flag

The Add Indirect (ADD@) instruction adds the value at the address in the specified address register to the value in the specified destination register, stores the result in the destination register, and sets or clears the Sign Flag, Zero Flag, Overflow Flag, and Carry Flag according to the result.

If prefixed with SDBD, this instruction will perform two indirect reads to build a 16-bit value for its first operand, and will always use exactly 10 clock cycles regardless of which register is used as the address register. See Double Byte Data for more details on how SDBD interacts with Indirect Mode.


   0000:0010:10aa:addd
where: ddd indicates the register containing the value to move such that: ddd == 000 indicates register R0 ddd == 001 indicates register R1 ddd == 010 indicates register R2 ddd == 011 indicates register R3 ddd == 100 indicates register R4 ddd == 101 indicates register R5 ddd == 110 indicates register R6 ddd == 111 indicates register R7
aaa indicates the register containing the address such that: aaa == 000 indicates direct mode ADD instruction aaa == 001 indicates register R1 aaa == 010 indicates register R2 aaa == 011 indicates register R3 aaa == 100 indicates register R4 aaa == 101 indicates register R5 aaa == 110 indicates register R6, which operates in stack mode aaa == 111 indicates register R7, alias for immediate mode ADDI
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