VBlank Interrupt - Revision history

BrandonE at 04:22, 17 December 2012

2012-12-17T04:22:06Z

Mr z: Protected "VBlank Interrupt" ([edit=autoconfirmed] (indefinite) [move=autoconfirmed] (indefinite))

2010-12-04T09:43:45Z

Protected "VBlank Interrupt" ([edit=autoconfirmed] (indefinite) [move=autoconfirmed] (indefinite))

Pingaso at 19:47, 12 January 2005

2005-01-12T19:47:36Z

Pingaso at 22:08, 11 January 2005

2005-01-11T22:08:09Z

Mr z: /* break convoluted sentence into multiple sentences; other wording tweaks for active voice */

2005-01-11T21:29:42Z

‎break convoluted sentence into multiple sentences; other wording tweaks for active voice

Pingaso at 18:53, 11 January 2005

2005-01-11T18:53:35Z

Pingaso at 18:52, 11 January 2005

2005-01-11T18:52:13Z

Mr z at 00:24, 11 January 2005

2005-01-11T00:24:06Z

Mr z at 00:22, 11 January 2005

2005-01-11T00:22:01Z

New page

The VBlank Interrupt (short for "Vertical Blanking Interrupt") is an interrupt signaled by the [[STIC]] when it has finished drawing the active display. It signals this interrupt as it begins to draw the solid border at the bottom of the screen. The VBlank Interrupt is important for two reasons:

* It provides a regular "pulse" upon which to base game timing and events.
* It signals the start of the [[VBlank Interval]], which controls access to STIC registers, [[GRAM]] and [[GROM]].

On NTSC Intellivisions, this interrupt occurs once every 14394 cycles. On PAL/SECAM Intellivisions, this interrupt occurs once every ?? cycles.

← Older revision		Revision as of 04:22, 17 December 2012
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	* It signals the start of the [[VBlank Interval]], which controls access to STIC registers, [[Graphics RAM]] and [[Graphics ROM]].		* It signals the start of the [[VBlank Interval]], which controls access to STIC registers, [[Graphics RAM]] and [[Graphics ROM]].

−	On NTSC Intellivisions, the [[STIC]] asserts this signal once every 14394 cycles, and holds it asserted for exactly 3791 [[CP1610]] clock cycles. On PAL/SECAM Intellivisions, the exact interrupt timing is unknown. In order to take the interrupt, the [[CP1610]]'s [[Interrupt Enable Flag]] must be set, and the CPU must encounter at least one interruptible instruction while the STIC asserts SR1. Otherwise, the CPU will drop the interrupt.	+	On NTSC Intellivisions, the [[STIC]] asserts this signal once every 14934 (Some sources say 14394) cycles, and holds it asserted for exactly 3791 [[CP1610]] clock cycles. On PAL/SECAM Intellivisions, the exact interrupt timing is unknown. In order to take the interrupt, the [[CP1610]]'s [[Interrupt Enable Flag]] must be set, and the CPU must encounter at least one interruptible instruction while the STIC asserts SR1. Otherwise, the CPU will drop the interrupt.

← Older revision		Revision as of 19:47, 12 January 2005
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−	[[Category:STIC]]	+	[[Category:STIC]][[Category:CP1610]]
−	[[Category:CP1610]]
	The [[STIC]] signals the VBlank Interrupt (short for "Vertical Blanking Interrupt") when it has finished drawing the active display, just as it begins to draw the solid border at the bottom of the screen. The STIC signals this interrupt by pulsing its SR1 output low. SR1 connects directly to the [[CP1610]]'s INTRM input.		The [[STIC]] signals the VBlank Interrupt (short for "Vertical Blanking Interrupt") when it has finished drawing the active display, just as it begins to draw the solid border at the bottom of the screen. The STIC signals this interrupt by pulsing its SR1 output low. SR1 connects directly to the [[CP1610]]'s INTRM input.

← Older revision		Revision as of 22:08, 11 January 2005
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		+	[[Category:STIC]]
		+	[[Category:CP1610]]
	The [[STIC]] signals the VBlank Interrupt (short for "Vertical Blanking Interrupt") when it has finished drawing the active display, just as it begins to draw the solid border at the bottom of the screen. The STIC signals this interrupt by pulsing its SR1 output low. SR1 connects directly to the [[CP1610]]'s INTRM input.		The [[STIC]] signals the VBlank Interrupt (short for "Vertical Blanking Interrupt") when it has finished drawing the active display, just as it begins to draw the solid border at the bottom of the screen. The STIC signals this interrupt by pulsing its SR1 output low. SR1 connects directly to the [[CP1610]]'s INTRM input.

@@ Line 1: / Line 1: @@
-The VBlank Interrupt (short for "Vertical Blanking Interrupt") is an interrupt signaled by the [[STIC]] by asserting low on SR1 (which is connected to the INTRM line on the [[CP1610]]) when it has finished drawing the active display, just as it begins to draw the solid border at the bottom of the screen.  The VBlank Interrupt is important for two reasons:
+The [[STIC]] signals the VBlank Interrupt (short for "Vertical Blanking Interrupt") when it has finished drawing the active display, just as it begins to draw the solid border at the bottom of the screen.  The STIC signals this interrupt by pulsing its SR1 output low.  SR1 connects directly to the [[CP1610]]'s INTRM input.
 * It provides a regular "pulse" upon which to base game timing and events.
 * It signals the start of the [[VBlank Interval]], which controls access to STIC registers, [[Graphics RAM]] and [[Graphics ROM]].
-On NTSC Intellivisions, the [[STIC]] stignals this interrupt once every 14394 cycles and it maintains this signal for exactly 3791 [[CP1610]] clock cycles.  On PAL/SECAM Intellivisions, the exact interrupt timing is unknown.  Note that if the [[Interrupt Enable Flag]] within the [[CP1610]] is clear for the entire duration of the signal from the [[STIC]], or if the [[CP1610]] simply never encounters an interruptible instruction during that time, the CP1610 will miss the interrupt altogether.
+On NTSC Intellivisions, the [[STIC]] asserts this signal once every 14394 cycles, and holds it asserted for exactly 3791 [[CP1610]] clock cycles.  On PAL/SECAM Intellivisions, the exact interrupt timing is unknown.  In order to take the interrupt, the [[CP1610]]'s [[Interrupt Enable Flag]] must be set, and the CPU must encounter at least one interruptible instruction while the STIC asserts SR1.  Otherwise, the CPU will drop the interrupt.

← Older revision		Revision as of 18:53, 11 January 2005
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	* It signals the start of the [[VBlank Interval]], which controls access to STIC registers, [[Graphics RAM]] and [[Graphics ROM]].		* It signals the start of the [[VBlank Interval]], which controls access to STIC registers, [[Graphics RAM]] and [[Graphics ROM]].

−	On NTSC Intellivisions, the [[STIC]] stignals this interrupt once every 14394 cycles and it maintains this signal for exactly 3791 [[CP1610]] clock cycles. On PAL/SECAM Intellivisions, the exact interrupt timing is unknown. Note that if the [[Interrupt Enable Flag]] within the [[CP1610]] is clear for the entire duration of the signal from the [[STIC]], or if the [[CP1610]] simply never encounters an interruptible instruction during that time, the CP1610 will miss the interrupt altogether~~. This has been noted as a problem in particular for the game [[Dreadnaught Factor]]~~.	+	On NTSC Intellivisions, the [[STIC]] stignals this interrupt once every 14394 cycles and it maintains this signal for exactly 3791 [[CP1610]] clock cycles. On PAL/SECAM Intellivisions, the exact interrupt timing is unknown. Note that if the [[Interrupt Enable Flag]] within the [[CP1610]] is clear for the entire duration of the signal from the [[STIC]], or if the [[CP1610]] simply never encounters an interruptible instruction during that time, the CP1610 will miss the interrupt altogether.

← Older revision	Revision as of 09:43, 4 December 2010
(No difference)

@@ Line 2: / Line 2: @@
 * It provides a regular "pulse" upon which to base game timing and events.
-* It signals the start of the [[VBlank Interval]], which controls access to STIC registers, [[GRAM]] and [[GROM]].
+* It signals the start of the [[VBlank Interval]], which controls access to STIC registers, [[Graphics RAM]] and [[Graphics ROM]].
 On NTSC Intellivisions, this interrupt occurs once every 14394 cycles.  On PAL/SECAM Intellivisions, this interrupt occurs once every ?? cycles.