Introducing the Instruction Set Part 2 - Revision history

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2010-12-04T08:41:45Z

Protected "Introducing the Instruction Set Part 2" ([edit=autoconfirmed] (indefinite) [move=autoconfirmed] (indefinite))

Mr z: /* Moving On */

2007-10-09T22:56:06Z

‎Moving On

Mr z: /* Moving On */

2007-10-08T23:08:08Z

‎Moving On

Mr z: /* Implied Operand Instructions */

2007-10-08T23:07:49Z

‎Implied Operand Instructions

Mr z at 23:01, 8 October 2007

2007-10-08T23:01:39Z

New page

[[Category:Programming]][[Category:Tutorial]]

This short part covers the Single Register Arithmetic instructions as well as the Implied Operand instructions. If you haven't read it already, please see [[Introducing the Instruction Set Part 1]].

= Single Register Arithmetic Instructions =

These instructions are fairly simple instructions that operate on a single register:

<TABLE BORDER>
<TR><TH>  [[TSTR]]  </TH><TD COLSPAN=2>Check sign, zero on a register </TD></TR>
<TR><TH>  [[CLRR]]  </TH><TD>Set a register to 0 </TD><TD> R = 0 </TD></TR>
<TR><TH>  [[INCR]]  </TH><TD>Increment a register </TD><TD> R = R + 1 </TD></TR>
<TR><TH>  [[DECR]]  </TH><TD>Decrement a register </TD><TD> R = R - 1 </TD></TR>
<TR><TH>  [[NEGR]]  </TH><TD>Negate a register </TD><TD> R = -R </TD></TR>
<TR><TH>  [[COMR]]  </TH><TD>1s complement a register </TD><TD> R = R XOR $FFFF </TD></TR>
<TR><TH>  [[ADCR]]  </TH><TD>Add carry bit to register </TD><TD> R = R + C </TD></TR>
</TABLE>

These instructions work equally on all 8 registers. That includes the program counter. For instance, "INCR R7" (aka. INCR PC) will skip the next instruction word. That can be useful for skipping single-word instructions. "DECR R7" (aka. DECR PC) is equivalent to "here: B here", but is one byte shorter.

Example: Consider the value of R0 at each step in this sequence as it executes:

CLRR R0 ; Clear R0: R0 = 0
INCR R0 ; Add 1 to R0: R0 = 1
DECR R0 ; Subtract 1 from R0: R0 = 0
COMR R0 ; 1s complement R0: R0 = $FFFF
NEGR R0 ; Negate R0: R0 = 1

The ADCR instruction is useful for extended precision arithmetic. The following example shows how to add the 32-bit number in R3:R2 to the 32-bit number in R1:R0. (R3 and R1 hold the upper halves of the 32-bit numbers, whereas R2 and R0 hold the lower halves.)
<CODE><pre>
; Add lower halves together. This generates a carry in 'C'
ADDR R2, R0

; Add carry into upper half of result
ADCR R1

; Now add upper halves together.
ADDR R3, R1
</pre></CODE>

= Implied Operand Instructions =

These instructions don't operate on any register:

<TABLE BORDER>
<TR><TH>  [[NOP]]  </TH><TD> No operation</TD></TR>
<TR><TH>  [[SETC]]  </TH><TD>Set carry flag</TD></TR>
<TR><TH>  [[CLRC]]  </TH><TD>Clear carry flag</TD></TR>
<TR><TH>  [[EIS]]  </TH><TD> Enable interrupts</TD></TR>
<TR><TH>  [[DIS]]  </TH><TD> Disable interrupts</TD></TR>
</TABLE>

SETC, CLRC and NOP are fairly self explanatory. EIS and DIS are also straightforward, though interrupts are beyond the scope of this tutorial. They are important, and I will cover them in a future tutorial.

@@ Line 60: / Line 60: @@
 * [[Introducing the Instruction Set Part 1]]:  The CPU, Memory and Registers; Primary Instructions and Addressing Modes
 <!--* [[Introducing the Instruction Set Part 2]]:  Single Register and Implied Operand Instructions-->
-* [[Introducing the Instruction Set Part 3]]:  Shift and Rotate Instructions
+* [[Introducing the Instruction Set Part 3]]:  Branches, Conditional Branches and Calls
-* [[Introducing the Instruction Set Part 4]]:  Branches, Conditional Branches and Calls
+* [[Introducing the Instruction Set Part 4]]:  Shift and Rotate Instructions
 Or, you can return to the [[Programming Tutorials]] index.

@@ Line 59: / Line 59: @@
 * [[Introducing the Instruction Set Part 1]]:  The CPU, Memory and Registers; Primary Instructions and Addressing Modes
-* [[Introducing the Instruction Set Part 2]]:  Single Register and Implied Operand Instructions
+<!--* [[Introducing the Instruction Set Part 2]]:  Single Register and Implied Operand Instructions-->
-<!--* [[Introducing the Instruction Set Part 3]]:  Shift and Rotate Instructions-->
+* [[Introducing the Instruction Set Part 3]]:  Shift and Rotate Instructions
 * [[Introducing the Instruction Set Part 4]]:  Branches, Conditional Branches and Calls
 Or, you can return to the [[Programming Tutorials]] index.

← Older revision		Revision as of 23:07, 8 October 2007
Line 53:		Line 53:

	SETC, CLRC and NOP are fairly self explanatory. EIS and DIS are also straightforward, though interrupts are beyond the scope of this tutorial. They are important, and I will cover them in a future tutorial.		SETC, CLRC and NOP are fairly self explanatory. EIS and DIS are also straightforward, though interrupts are beyond the scope of this tutorial. They are important, and I will cover them in a future tutorial.
		+
		+	= Moving On =
		+
		+	At this point, you may wish to continue with the remaining parts of this tutorial:
		+
		+	* [[Introducing the Instruction Set Part 1]]: The CPU, Memory and Registers; Primary Instructions and Addressing Modes
		+	* [[Introducing the Instruction Set Part 2]]: Single Register and Implied Operand Instructions
		+	<!--* [[Introducing the Instruction Set Part 3]]: Shift and Rotate Instructions-->
		+	* [[Introducing the Instruction Set Part 4]]: Branches, Conditional Branches and Calls
		+
		+	Or, you can return to the [[Programming Tutorials]] index.

← Older revision	Revision as of 08:41, 4 December 2010
(No difference)