Bus Phases - Revision history

Mr z: Protected "Bus Phases" ([edit=autoconfirmed] (indefinite) [move=autoconfirmed] (indefinite))

2010-12-04T08:08:53Z

Protected "Bus Phases" ([edit=autoconfirmed] (indefinite) [move=autoconfirmed] (indefinite))

Mr z: /* Interrupt Processing */

2006-05-06T14:54:04Z

‎Interrupt Processing

Mr z: /* Interrupt Processing */

2005-01-24T01:53:59Z

‎Interrupt Processing

Mr z: /* Transaction Types */

2005-01-23T22:39:25Z

‎Transaction Types

Mr z at 22:38, 23 January 2005

2005-01-23T22:38:31Z

Mr z: /* Bus Phases */

2005-01-18T06:58:56Z

‎Bus Phases

Mr z: /* Bus Phases */

2005-01-18T06:51:20Z

‎Bus Phases

Mr z: /* reword table for active voice */

2005-01-15T15:30:23Z

‎reword table for active voice

Mr z at 20:04, 14 January 2005

2005-01-14T20:04:25Z

Mr z at 20:03, 14 January 2005

2005-01-14T20:03:21Z

Show changes

@@ Line 283: / Line 283: @@
 ===Interrupt Processing===
 <TABLE BORDER=1 WIDTH=100%>
 <TR>

@@ Line 326: / Line 326: @@
 <TH BGCOLOR=#CCDDEE><TT>NACT</TT></TH>
 <TD BGCOLOR=#CCDDEE>The device deasserts the bus, and no other bus activity occurs during this cycle. </TD>
 </TR>
 </TABLE>

@@ Line 79: / Line 79: @@
 ==Transaction Types==
-<P>The CP-1600's bus transactions typically last between 4 and 7 CPU cycles.  Half of these cycles are <TT>NACT</TT> cycles, inserted as spacing cycles between the activity cycles.  As a general rule, there is a <TT>NACT</TT> cycle inserted after every cycle EXCEPT in two specific cases.  The first is between <TT>DW</TT> and <TT>DWS,</TT> which always occur back-to-back.  The second is during an indirect access after an <TT>SDBD</TT> instruction, where the CPU omits <TT>NACT</TT> states after both <TT>DTB</TT>s.</P>
+<P>The CP-1600's bus transactions typically last between 4 and 7 CPU cycles.  Half of these cycles are <TT>NACT</TT> cycles, inserted as spacing cycles between the activity cycles.  As a general rule, there is a <TT>NACT</TT> cycle inserted after every cycle  <em>except</em> in two specific cases.  The first is between <TT>DW</TT> and <TT>DWS,</TT> which always occur back-to-back.  The second is during an indirect access after an <TT>SDBD</TT> instruction, where the CPU omits <TT>NACT</TT> states after both <TT>DTB</TT>s.</P>
 <P>The tables below illustrate the various bus transations, complete with a cycle-by-cycle description of the transaction.</P>

@@ Line 3: / Line 3: @@
 * Whether the value's an address or data
 * Whether the current access is a read or a write
+<br/>
 ==Bus Phases==
-The Intellivision is built around a bidirectional, multiplexed address/data bus.  This means the same lines are used alternately for address and data, and that each transaction is divided into multiple phases.  Hardware external to the CPU must latch the address for a transaction while it's available.  A future bus phase will read or write data at that address.  Separate control lines indicate what bus phase is currently active.
+The Intellivision is built around a bidirectional, multiplexed address/data bus.  This means the same lines are used alternately for address and data, and that each transaction is divided into multiple phases.  Hardware external to the CPU must latch the address for a transaction while it's available.  A future bus phase will read or write data at that address.  The BC1, BC2 and BDIR control lines indicate what bus phase is currently active.
 Most devices associated with the Intellivision latch addresses internally.  The only exceptions appear to be the [[Graphics RAM]] and [[Scratchpad RAM]], which rely on the [[Graphics ROM]] and [[Executive ROM]] to latch addresses for them, respectively.   In the descriptions that follow, references to "Address Register" refer to this latch.

@@ Line 5: / Line 5: @@
 ==Bus Phases==
 The following table describes the CP1610's various bus phases.
@@ Line 57: / Line 61: @@
          <TD><B>D</B>ata <B>W</B>rite
          </TD>
-         <TD ROWSPAN=2>The <TT>DW</TT> and <TT>DWS</TT> bus phases together form the write cycle.  The CPU always issues DW and DWS consecutively, while it holds the data it's writing stable across both cycles.  Thus, the CP-1600 allows two full CPU cycles for external RAM to latch the data.  The addressed device can sample the data on either cycle, or use both if it needs it.
+         <TD ROWSPAN=2>The <TT>DW</TT> and <TT>DWS</TT> bus phases together form the write cycle.  The CPU always issues <TT>DW</TT> and <TT>DWS</TT> consecutively, while it holds the data it's writing stable across both cycles.  Thus, the CP-1600 allows two full CPU cycles for external RAM to latch the data.  The addressed device can sample the data on either cycle, or use both if it needs it.
          </TD>
@@ Line 69: / Line 73: @@
          <TH>1</TH><TH>1</TH><TH>1</TH><TH><TT>INTAK</TT></TH>
          <TD><B>INT</B>errupt <B>A</B>c<B>K</B>nowledge</TD>
-         <TD>The CPU issues <TT>INTAK</TT> in response to an interrupt.  During the phase, the CPU places the current stack pointer value on the bus as it prepares to "push" the current program counter on the stack.  Devices are expected to treat <TT>INTAK</TT> similarly to a BAR bus phase.  Indeed, the Intellivision Master Component only lets the 16-bit [[System RAM]] see the <TT>INTAK</TT> bus phase.  The Intellivision remaps <TT>INTAK</TT> to <TT>BAR</TT> with discrete logic for all other devices.  The [[System RAM]] uses <TT>INTAK</TT> to trigger a special [[Bus Copy]] mode in addition to latching the current address.</TD>
+         <TD>The CPU issues <TT>INTAK</TT> in response to an interrupt.  During the phase, the CPU places the current stack pointer value on the bus as it prepares to "push" the current program counter on the stack.  Devices are expected to treat <TT>INTAK</TT> similarly to a <TT>BAR</TT> bus phase.  Indeed, the Intellivision Master Component only lets the 16-bit [[System RAM]] see the <TT>INTAK</TT> bus phase.  The Intellivision remaps <TT>INTAK</TT> to <TT>BAR</TT> with discrete logic for all other devices.  The [[System RAM]] uses <TT>INTAK</TT> to trigger a special [[Bus Copy]] mode in addition to latching the current address.</TD>
      </TR>
 </TABLE>

← Older revision	Revision as of 08:08, 4 December 2010
(No difference)

@@ Line 29: / Line 29: @@
          <TD><B>A</B>ddress <B>D</B>ata to <B>A</B>ddress <B>R</B>egister
          </TD>
-         <TD>The CPU issues <TT>ADAR</TT> during a Direct Addressing Mode instruction.  Prior to ADAR, a previous <TT>BAR</TT> or <TT>ADAR</TT> latches an address in all the device's address registers.  During this phase, the currently selected device responds with its data on the bus.  At the end of this phase, all devices should latch that data as the next "current address."  A subsequent <TT>DTB</TT>, <TT>DW</TT>, <TT>DWS</TT> or <TT>ADAR</TT> will access the newly selected location.  The CPU asserts nothing during this phase.  Rather, it expects the currently addressed device to inform the rest of the machine of the address for the next access.
+         <TD>The CPU issues <TT>ADAR</TT> during a Direct Addressing Mode instruction.  Prior to <TT>ADAR</TT>, a previous <TT>BAR</TT> or <TT>ADAR</TT> latches an address in all the device's address registers.  During this phase, the currently selected device responds with its data on the bus.  At the end of this phase, all devices should latch that data as the next "current address."  A subsequent <TT>DTB</TT>, <TT>DW</TT>, <TT>DWS</TT> or <TT>ADAR</TT> will access the newly selected location.  The CPU asserts nothing during this phase.  Rather, it expects the currently addressed device to inform the rest of the machine of the address for the next access.
          </TD>
      </TR>

@@ Line 22: / Line 22: @@
          <TD><B>N</B>o <B>ACT</B>ion
          </TD>
-         <TD>During this stage, no device is active on the bus. DB0 through DB15 are allowed to float, with their previous driven value fading away during this phase.
+         <TD>During this stage, no device is active on the bus. DB0 through DB15 float to all ones (1), with their previous driven value fading away during this phase.
          </TD>
      </TR>
@@ Line 29: / Line 29: @@
          <TD><B>A</B>ddress <B>D</B>ata to <B>A</B>ddress <B>R</B>egister
          </TD>
-         <TD>This bus phase is issued by the CPU during a Direct Addressing Mode instruction.  Prior to this phase, an address will have been latched in a device by a prior <TT>BAR</TT> or <TT>ADAR</TT> bus phase.  Then, during this phase, the currently selected device responds with its data on the bus, and at the end of this phase, all devices should latch this address as the address for the next memory access (<TT>DTB</TT>, <TT>DW</TT>, or <TT>DWS</TT> phases).  The CPU asserts nothing during this phase -- rather, it expects the currently addressed device to inform the rest of the machine of the address for the next access.
+         <TD>The CPU issues <TT>ADAR</TT> during a Direct Addressing Mode instruction.  Prior to ADAR, a previous <TT>BAR</TT> or <TT>ADAR</TT> latches an address in all the device's address registers.  During this phase, the currently selected device responds with its data on the bus.  At the end of this phase, all devices should latch that data as the next "current address."  A subsequent <TT>DTB</TT>, <TT>DW</TT>, <TT>DWS</TT> or <TT>ADAR</TT> will access the newly selected location.  The CPU asserts nothing during this phase.  Rather, it expects the currently addressed device to inform the rest of the machine of the address for the next access.
          </TD>
      </TR>
@@ Line 36: / Line 36: @@
          <TH>0</TH><TH>1</TH><TH>0</TH><TH><TT>IAB</TT></TH>
          <TD><B>I</B>nterrupt <B>A</B>ddress to <B>B</B>us</TD>
-         <TD>This bus phase is entered during interrupt processing, after the current program counter has been written to the stack. It's also entered into on the first cycle after coming out of RESET.  During this phase, an external device should assert the address of the Interrupt or RESET vector as appropriate. The CPU then moves this address into the program counter and resumes execution.
+         <TD>The CPU issues this phase in response to an interrupt, after it wrties the current program counter to the stack.  The CPU also issues <TT>IAB</TT> on the first cycle after coming out of RESET.  During this phase, an external device asserts the address of the Interrupt or RESET vector as appropriate. The CPU moves this address into the program counter and resumes execution.
          </TD>
      </TR>
@@ Line 42: / Line 42: @@
          <TH>0</TH><TH>1</TH><TH>1</TH><TH><TT>DTB</TT></TH>
          <TD><B>D</B>ata <B>T</B>o <B>B</B>us</TD>
-         <TD>This phase is entered during a read cycle.  During this phase, the currently addressed device should assert its data on the bus.  The CPU then reads this data.
+         <TD>The CPU issues this phase during a read cycle.  In response to <TT>DTB</TT>, the currently addressed device asserts its data on the bus.  The CPU reads this data.
          </TD>
      </TR>
@@ Line 49: / Line 49: @@
          <TD><B>B</B>us to <B>A</B>ddress <B>R</B>egister
          </TD>
-         <TD>During this phase, the CPU asserts the address for the current memory access.  All devices on the bus are expected to latch this address and perform address decoding at this time.
+         <TD>During this phase, the CPU asserts the address for the current memory access.  All devices on the bus latch and decode the address at this time.
          </TD>
      </TR>
@@ Line 57: / Line 57: @@
          <TD><B>D</B>ata <B>W</B>rite
          </TD>
-         <TD ROWSPAN=2>The <TT>DW</TT> and <TT>DWS</TT> bus phases initiate a write cycle.  They always occur together on adjacent cycles, with data remaining stable on the bus across the transition from <TT>DW</TT> to <TT>DWS.</TT>  During these phases, the data being written is available for external memories to latch.  The CP-1600 allows two full CPU cycles for external RAM to latch the data.
+         <TD ROWSPAN=2>The <TT>DW</TT> and <TT>DWS</TT> bus phases together form the write cycle.  The CPU always issues DW and DWS consecutively, while it holds the data it's writing stable across both cycles.  Thus, the CP-1600 allows two full CPU cycles for external RAM to latch the data.  The addressed device can sample the data on either cycle, or use both if it needs it.
          </TD>
@@ Line 69: / Line 69: @@
          <TH>1</TH><TH>1</TH><TH>1</TH><TH><TT>INTAK</TT></TH>
          <TD><B>INT</B>errupt <B>A</B>c<B>K</B>nowledge</TD>
-         <TD>The CPU enters this bus phase on the first cycle of interrupt processing.  During the phase, the CPU places the current stack pointer value on the bus as it prepares to "push" the current program counter on the stack.  Devices are expected to treat <TT>INTAK</TT> similarly to a BAR bus phase.  Indeed, on the Intellivision Master Component, only the 16-bit System RAM sees the <TT>INTAK</TT> bus phase.  It uses this bus phase to trigger a special bus-copy mode as well as for latching the current address.  For all other devices in the system, <TT>INTAK</TT> is remapped to <TT>BAR</TT> by some discrete logic, and so is processed as a normal addressing cycle elsewhere.</TD>
+         <TD>The CPU issues <TT>INTAK</TT> in response to an interrupt.  During the phase, the CPU places the current stack pointer value on the bus as it prepares to "push" the current program counter on the stack.  Devices are expected to treat <TT>INTAK</TT> similarly to a BAR bus phase.  Indeed, the Intellivision Master Component only lets the 16-bit [[System RAM]] see the <TT>INTAK</TT> bus phase.  The Intellivision remaps <TT>INTAK</TT> to <TT>BAR</TT> with discrete logic for all other devices.  The [[System RAM]] uses <TT>INTAK</TT> to trigger a special [[Bus Copy]] mode in addition to latching the current address.</TD>
      </TR>
 </TABLE>